鈩?/div>
input pull-down resistors
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E136 are 6-bit synchronous, presettable,
cascadable universal counters. These devices generate
a look-ahead-carry output and accept a look-ahead-carry
input. These two features allow for the cascading of
multiple E136s for wider bit width counters that operate
at very nearly the same frequency as the stand-alone
counter.
The CL
OUT
output will pulse LOW for one clock cycle
one count before the E136 reaches terminal count. The
C
OUT
output will pulse LOW for one clock cycle when
the counter reaches terminal count. For more information
on utilizing the look-ahead-carry features of the device,
please refer to the applications section of this data sheet.
The differential C
OUT
output facilitates the E136's use in
programmable divider and self-stopping counter
applications.
Unlike the H136 and other similar universal counter
designs, the E136 carry-out and look-ahead-carry-out
signals are registered on chip. This design alleviates the
glitch problem seen on many counters where the carry-
out signals are merely gated. Because of this architecture,
there are some minor functional differences between the
E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet
carefully. Note specifically (see block diagram) the
operation of the carry-out outputs and the look-ahead-
carry-in input when utilizing the Master Reset.
When left open, all of the input pins will be pulled
LOW via an input pulldown resistor. The Master Reset is
an asynchronous signal which, when asserted, will force
the Q outputs LOW.
The Q outputs need not be terminated for the E136 to
function properly. In fact, if these outputs will not be
used in a system, it is recommended that they be left
open to save power and minimize noise. This practice
will minimize switching noise which can reduce the
maximum count frequency of the device, or significantly
reduce margins against other noise in the system.
PIN CONFIGURATION
V
CCO
V
CCO
25 24 23 22 21
Q
5
20 19
18
17
Q
4
D
3
D
4
D
5
D
2
S
2
S
1
V
EE
CLK
C
IN
CL
IN
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
3
Q
2
V
CC
V
CCO
C
OUT
C
OUT
CL
OUT
PLCC
TOP VIEW
J28-1
16
15
14
13
12
D
1
V
CCO
MR
Q
0
D
0
PIN NAMES
Pin
D
0
鈥揇
5
Q
0
鈥換
5
S
1
, S
2
MR
CLK
C
OUT
, C
OUT
CL
OUT
C
IN
CL
IN
V
CCO
Function
Preset Data Inputs
Differential Data Outputs
Mode Control Pins
Master Reset
Clock Input
Carry Out Output (Active LOW)
Look-Ahead-Carry Output
Carry-In Input (Active LOW)
Look-Ahead-Carry Input
V
CC
to Output
V
CCO
Q
1
Rev.: C
Amendment: /1
1
Issue Date: February, 1998
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