450ps max. Propagation Delay
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E116
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E116 are quint differential line receivers
designed for use in new, high-performance ECL systems.
These devices have emitter-follower outputs and an
internally generated reference supply (V
BB
) for single-
ended reception.
Active current sources combined with Micrel-Synergy鈥檚
ASSET鈩?technology provide the receivers with excellent
common mode noise rejection.
The receiver design features clamp circuitry to cause a
defined output state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes LOW,
while the Q output goes HIGH.
If both inverting and non-inverting inputs are at equal
potential, the receiver does
not
go to a defined state, but
rather shares current in normal differential amplifier fashion,
producing output voltage levels midway between HIGH
and LOW.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01
碌F
capacitor.
For higher bandwidth, please refer to the SY10/100E416
device.
BLOCK DIAGRAM
D
0
D
0
D
1
D
1
D
2
D
2
D
3
D
3
D
4
D
4
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
PIN CONFIGURATION
V
CCO
Q
4
V
BB
25
24 23 22 21 20 19
18
17
D
3
D
2
D
2
V
EE
V
BB
D
0
D
0
D
4
D
4
Q
4
D
3
Q
4
V
CCO
Q
4
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
3
Q
3
V
CC
Q
2
Q
2
V
CCO
Q
1
PLCC
TOP VIEW
J28-1
16
15
14
13
12
PIN NAMES
V
CCO
Q
0
Pin
D
0
, D
0
-D
4
, D
4
Q
0
, Q
0
-Q
4
, Q
4
V
BB
V
CCO
Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output
V
CC
to Output
V
CCO
Q
0
Q
1
Rev.: E
D
1
D
1
Amendment: /0
1
Issue Date: November, 1998
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2
3
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