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SY10E112JITR Datasheet

  • SY10E112JITR

  • QUAD DRIVER

  • 74.70KB

  • 4頁(yè)

  • MICREL   MICREL

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QUAD
DRIVER
SY10E112
SY100E112
FEATURES
s
600ps max. propagation delay
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
Common enable input
s
Fully compatible with industry standard 10KH, 100K
I/O levels
s
Internal 75K
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E112
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E112 are quad drivers designed for use
in new, high-performance ECL systems. The E112 has two
pairs of OR/NOR outputs from each gate and a common,
buffered enable input. The data input can also be used as
an ECL memory address fan-out driver, although the E111
is designed specifically for this purpose, and offers lower
skew than the E112. For memory address driver applications
where scan capabilities are required, please refer to the
SY10/100E212 device.
BLOCK DIAGRAM
Q
0a
Q
0b
Q
0a
Q
0b
PIN CONFIGURATION
V
CCO
Q
2b
Q
2a
Q
3b
V
CCO
D
0
25 24 23 22 21 20 19
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
3a
Q
3b
Q
3a
Q
2b
Q
2a
V
CC
Q
1b
Q
1a
Q
1b
Q
1a
Q
1a
D
1
Q
1b
Q
1a
Q
1b
Q
2a
D
2
Q
2b
Q
2a
Q
2b
Q
3a
D
3
Q
3b
Q
3a
Q
3b
D
3
D
2
V
EE
D
1
D
0
EN
PLCC
TOP VIEW
J28-1
16
15
14
13
12
V
CCO
Q
0a
Q
0b
PIN NAMES
Pin
Function
Data Inputs
Enable Input
True Outputs
Inverting Outputs
V
CC
to Output
EN
D
0
-D
3
EN
Q
na
, Q
nb
Q
na
, Q
nb
V
CCO
V
CCO
Rev.: D
NC
Q
0a
Q
0b
Amendment: /2
1
Issue Date: May, 1998

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