鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E111
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of 鈥渂asic鈥?/div>
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50鈩? even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01碌F
capacitor.
BLOCK DIAGRAM
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
IN
IN
EN
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
V
BB
Q
8
Q
4
Q
4
Q
5
Rev.: B
Amendment: /2
1
Issue Date: February, 1998
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