1500ps max. delay from CLK
1500ps max. delay from CLK
鈩?/div>
input pull-down resistors
s
Voltage and temperature compensation for improved
noise immunity
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Available in 28-pin PLCC package
DESCRIPTION
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS
0
鈥?BUS
4
) are
specified for driving a 25 ohm bus and the receive outputs
(Q
0
鈥?Q
4
) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN
0
4
) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK
1
) which is common to all five bus driver
registers; and a separate clock (CLK
2
) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK
1
and
data on the bus is clocked into the Receiver register by
a positive transition of CLK
2
. A high on the Master Reset
clears all registers.
PIN CONFIGURATION
PIN NAMES
Pin
Function
Bus Enable Inputs
Data Inputs
Bus Driver Clock Input
Receive Register Clock
Master Reset
Bus Receive Outputs
Bus Outputs
BUSEN
3
D
4
BUSEN
4
BUSEN
0鈥?
BUS
4
V
CCA
Q
4
D
3
D
0
鈥?D
4
CLK
1
CLK
2
18
17
25 24 23 22 21 20 19
MR
CLK
2
CLK
1
V
EE
D
2
BUSEN
2
D
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
3
BUS
3
V
CC
Q
2
BUS
2
V
CCA
Q
1
MR
Q
0
鈥?Q
4
BUS
0鈥?
TOP VIEW
PLCC
J28-1
16
15
14
13
12
BUSEN
1
D
0
BUSEN
0
Q
0
BUS
0
V
CCA
BUS
1
Rev.: E
Amendment: /0
1
Issue Date: August, 1998
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2
3
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