鈩?/div>
input pull-down resistors
s
Available in 16-pin SOIC package
DESCRIPTION
The SY100S834/L is low skew (梅1,
梅2, 梅4)
or (梅2,
梅4, 梅8)
clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the V
BB
output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01碌F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (F
SEL
) input is used to determine
what clock generation chip function is. When FS
EL
input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FS
EL
input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
PIN CONFIGURATION/BLOCK DIAGRAM
Q
0
1
Q
0
2
Q
梅1
or
梅2
16
V
CC
R
15
Q
D
R
EN
V
CC
3
Q
1
4
Q
14
F
SEL
13
CLK
梅2
or
梅4
Q
1
5
V
CC
6
Q
2
Q
2
7
R
12
CLK
11
V
BB
10
MR
V
EE
Q
8
梅4
or
梅8
R
9
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
F
SEL
EN
MR
V
BB
Q
0
Q
1
Q
2
Function
Differential Clock Inputs
Function Select
Synchronous Enable
Master Reset
Reference Output
Differential
梅1
or
梅2
Outputs
Differential
梅2
or
梅4
Outputs
Differential
梅4
or
梅8
Outputs
TRUTH TABLE
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q
0鈥?
Reset Q
0鈥?
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
F
SEL
L
H
1
Q
0
Outputs
Divide by 2
Divide by 1
Q
1
Outputs
Divide by 4
Divide by 2
Q
2
Outputs
Divide by 8
Divide by 4
Rev.: F
Amendment: /0
Issue Date: September, 1999
MICREL
1
2
3
4
