鈩?/div>
PECL input pull-down resistors
s
Available in 16-pin SOIC package
DESCRIPTION
The SY100S815 is a low skew 1-to-4 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin T
EN
.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of 鈥渂asic鈥?/div>
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50鈩? even if only one side is being used. In
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
BLOCK DIAGRAM
Q
0
Q
0
Q
1
E
IN
E
IN
0
Q
2
Q
2
T
IN
1
Q
3
Q
3
Q
1
PIN CONFIGURATION
T
EN
V
CC
E
IN
T
IN
1
2
3
4
5
6
7
8
16
15
14
E
IN
T
EN
V
EE
PIN NAMES
Pin
E
IN
, E
IN
T
IN
T
EN
Q
0
, Q
0
鈥?Q
3
, Q
3
V
CC
V
EE
Function
Differential PECL Input Pair
TTL Input
TTL Input Enable
Differential PECL Outputs
PECL V
CC
(+5.0V)
PECL Ground (0V)
Q
3
Q
3
Q
2
Q
2
V
CCO
TOP VIEW
SOIC
Z16-1
13
Q
0
12
Q
0
11
Q
1
10
9
Q
1
V
CCO
Rev.: F
Amendment: /0
1
Issue Date: October, 1998
MICREL
1
2
3
4
