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SY100S391JCTR Datasheet

  • SY100S391JCTR

  • LOW-POWER HEX TTL-TO-PECL TRANSLATOR

  • 113.06KB

  • 6頁

  • MICREL   MICREL

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LOW-POWER
HEX TTL-TO-PECL
TRANSLATOR
FEATURES
s
Operates from a single +5V supply
s
Differential PECL outputs
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S391
DESCRIPTION
The SY100S391 is a hex TTL-to-PECL translator for
converting TTL logic levels to 100K logic levels. The unique
feature of this translator is the ability to do this translation
using only one +5V supply. The differential outputs allow
each circuit to be used as an inverting/non-inverting translator,
or as a differential line driver. A common enable (E), when
LOW, holds all inverting outputs HIGH and all non-inverting
inputs LOW.
The SY100S391 is ideal for those mixed PECL/TTL
applications which only have a +5V supply available. When
used in the differential mode, the S391, due to its high
common mode rejection, overcomes voltage gradients
between the TTL and PECL ground systems.
BLOCK DIAGRAM
E
PIN CONFIGURATIONS
D
0
Q
0
GNDS
D
0
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
D
2
GND TTL
GND PECL
GNDS
GND PECL
E
D
3
12
13
14
15
16
17
18
D
1
Q
0
D
1
11 10 9 8 7 6 5
4
3
Top View
PLCC
J28-1
2
1
28
27
26
19 20 21 22 23 24 25
Q
2
Q
2
V
CCA
V
CC
V
CC
Q
3
Q
3
D
2
D
3
E
GND PECL
GND PECL
GND TTL
D
5
Q
5
GNDS
Q
5
Q
4
Q
4
D
4
D
4
Q
1
Q
1
D
3
D
5
D
4
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
D
2
D
1
D
0
Q
0
Q
0
Q
1
Q
1
PIN NAMES
Pin
D
0
鈥?D
5
Q
0
鈥?Q
5
Q
0
鈥?Q
5
E
V
CCA
Function
Data Inputs (TTL)
Data Outputs (PECL)
D
5
Q
5
Q
5
Q
4
Q
4
13
7 8 9 10 11 12
Q
3
Inverting Data Outputs (PECL)
Enable Input (TTL)
V
CCO
for ECL Outputs
V
CC
V
CCA
Rev.: G
Q
2
Q
2
Amendment: /0
1
Q
3
Issue Date: July, 1999

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