Max. propagation delay of 1200ps
min. of 鈥?2mA
鈩?/div>
input pull-down resistors
s
60% faster than National or Signetics
s
Approximately 40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S370
DESCRIPTION
The SY100S370 is a universal demultiplexer/decoder
that can be used as either a dual 1-of-4 decoder or as a
single 1-of-8 decoder and is designed for use in high-
performance ECL systems. The Mode control (M) input
determines the function. In the dual 1-of-4 mode, each 4-
input group has a pair of active-LOW Enable (E) inputs.
The Enable pins are assigned such that in the single 1-of-
8 mode they can be tied together in pairs to result in two
active-LOW Enable inputs. E
1a
will be tied to E
1b
and E
2a
to E
2b
.
The auxiliary inputs (H
n
) are used to determine whether
the outputs are active-HIGH or active-LOW. The address
inputs for the dual 1-of-4 mode are A
0a
, A
1a
, A
0b
. A
2a
is
unused. In the 1-of-8 mode, the address inputs are A
0a
,
A
1a
, A
2a
. The inputs on the device have 75K鈩?pull-down
resistors.
PIN CONFIGURATIONS
M
A
1a
V
EES
A
2a
A
0a
Z
1a
(Z
1
)
Z
2a
(Z
2
)
PIN NAMES
Pin
A
na
, A
nb
E
na
, E
nb
M
H
a
H
b
H
c
Z
0
鈥?Z
7
Z
na
, Z
nb
V
EES
V
CCA
Function
Address Inputs (n = 0,1,2)
Enable Inputs (n = 1,2)
Mode Control Input
Z
0
鈥?Z
3
(Z
0a
鈥?Z
3a
) Polarity Select Input
Z
4
鈥?Z
7
(Z
0b
鈥?Z
3b
) Polarity Select Input
Common Polarity Select Input
Single 1-of-8 Data Outputs
Dual 1-of-4 Data Outputs (n = 1...4)
V
EE
Substrate
V
CCO
for ECL Outputs
E
1a
E
1b
V
EE
V
EES
E
2b
E
2a
H
a
12
13
14
15
16
17
18
11 10 9 8 7 6 5
4
3
2
1
28
27
26
Z
0a
(Z
0
)
Z
3a
(Z
3
)
V
CCA
V
CC
V
CC
Z
1b
(Z
5
)
Z
2b
(Z
6
)
Top View
PLCC
J28-1
19 20 21 22 23 24 25
H
b
A
0b
A
1b
Z
3b
(Z
7
)
Z
0b
(Z
4
)
V
EES
H
c
E
2a
E
2b
V
EE
E
1b
H
c
H
b
A
0b
A
1b
Z
3b
(Z
7
)
Z
0b
(Z
4
)
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
E
1a
H
a
A
2a
M
A
1a
A
0a
Z
1a
(Z
1
)
Z
2a
(Z
2
)
13
7 8 9 10 11 12
Z
2b
(Z
6
)
Z
1b
(Z
5
)
V
CC
Z
3a
(Z
3
)
Z
0a
(Z
0
)
Rev.: G
Amendment: /0
Issue Date: July, 1999
1
V
CCA
1
2
3
4
5
6
7
