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SY100S364JCTR Datasheet

  • SY100S364JCTR

  • 16-INPUT MULTIPLEXER

  • 5頁(yè)

  • MICREL   MICREL

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16-INPUT
MULTIPLEXER
FEATURES
s
Max. propagation delay of 1300ps
s
I
EE
min. of 鈥?3mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
70% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
11 10 9 8 7 6 5
I
15
S
0
V
EE
V
EES
S
1
S
2
S
3
12
13
14
15
16
17
18
4
3
2
1
28
27
26
I
8
Z
V
CCA
V
CC
V
CC
I
7
I
6
SY100S364
DESCRIPTION
The SY100S364 is a 16-input multiplexer designed for
use in high-performance ECL systems. The four Data
Select inputs (S
0
, S
1
, S
2
, S
3
) determine the bit from the 16
inputs (I
n
) that will be passed on to the output as shown in
the Truth Table. The output data polarity is the same as the
input. The inputs on the device have 75K鈩?pull-down
resistors.
PIN CONFIGURATIONS
I
13
I
12
V
EES
I
14
I
11
I
10
I
9
BLOCK DIAGRAM
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
S
3
I
7
I
6
S
2
I
5
I
4
S
1
I
3
I
2
S
0
I
1
I
0
Z
Top View
PLCC
J28-1
19 20 21 22 23 24 25
S
2
S
1
V
EE
S
3
V
EES
I
0
I
1
I
2
I
3
I
4
I
5
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
S
0
I
15
I
1
I
2
I
3
I
4
I
5
I
0
I
14
I
13
I
12
I
11
I
10
I
9
13
7 8 9 10 11 12
I
7
V
CC
V
CCA
Z
I
8
I
6
Rev.: G
Amendment: /0
1
Issue Date: July, 1999

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