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SY100S363FC Datasheet

  • SY100S363FC

  • DUAL 8-INPUT MULTIPLEXER

  • 6頁

  • MICREL   MICREL

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DUAL 8-INPUT
MULTIPLEXER
SY100S363
FEATURES
s
Max. propagation delay of 900ps
s
I
EE
min. of 鈥?2mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
60% faster than Fairchild 300K at lower power
s
Function and pinout compatible with Fairchild F100K
DESCRIPTION
The SY100S363 is a dual 8-input multiplexer designed
for use in new, high-performance ECL systems. The
three Data Select inputs (S
0
, S
1
, S
2
) determine the bits
from each of the inputs (A
n
, B
n
) that will be passed on
through the two outputs. The same bit will be selected
from the two groups of 8 inputs. The inputs on this
device have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
A
5
A
4
V
EES
A
6
A
3
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
A
7
S
0
V
EE
V
EES
S
1
S
2
B
7
12
13
14
15
16
17
18
11 10 9 8 7 6 5
4
3
2
1
28
27
26
A
a
Z
a
V
CCA
V
CC
V
CC
Z
b
B
0
BLOCK DIAGRAM
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
2
Z
a
Top View
PLCC
J28-1
19 20 21 22 23 24 25
A
2
A
1
S
2
S
1
V
EE
B
7
S
0
B
6
B
5
B
4
V
EES
B
3
B
2
B
1
B
6
B
5
B
4
B
3
B
2
B
1
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
A
7
A
6
A
5
A
4
A
3
A
2
A
1
13
7 8 9 10 11 12
B
0
S
1
S
0
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Z
b
V
CC
V
CCA
Rev.: G
Z
a
A
0
Amendment: /0
1
Z
b
Issue Date: July, 1999

SY100S363FC 產(chǎn)品屬性

  • 15

  • 集成電路 (IC)

  • 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器

  • 100S

  • 多路復(fù)用器

  • 2 x 8:1

  • 1

  • -

  • 雙電源

  • 4.2 V ~ 5.5 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 24-CQFlatpack，Cerpack

  • 24-CerPack

  • 管件

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