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SY100S355JCTR Datasheet

  • SY100S355JCTR

  • QUAD MULTIPLEXER/LATCH

  • 7頁

  • MICREL   MICREL

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QUAD
MULTIPLEXER/LATCH
FEATURES
s
Max. propagation delay of 1100ps
s
Max. enable to output delay of 1400ps
s
I
EE
min. of 鈥?0mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
50% faster than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S355
DESCRIPTION
The SY100S355 offers four transparent latches with
differential outputs and is designed for use in high-
performance ECL systems. The Select inputs (S
0
, S
1
)
select one of the two sources of input data (D
0
or D
1
) to the
latch. The Select inputs can also force the outputs to a logic
LOW when the latch is in the transparent mode. The
latches are in the transparent mode when both Enables
(E
1
, E
2
) are at a logic LOW state. In the transparent mode,
the Select inputs can pass an input logic HIGH from D
0
or
D
1
to the output.
If the Select inputs are tied together, then input data from
either D
0
or D
1
is always passed through. A rising edge on
either Enable input will latch the outputs with the most
recent data at the latch inputs being stored. The Master
Reset (MR) input overrides all other inputs and takes the Q
outputs to a logic LOW. The inputs on this device have
75K鈩?pull-down resistors.
BLOCK DIAGRAM
S
0
S
1
D
0a
D
D
1a
E
CD
D
0b
D
D
1b
E
CD
D
0c
D
D
1c
E
CD
D
0d
Q
c
Q
Q
c
Q
b
Q
Q
b
Q
a
Q
Q
a
PIN CONFIGURATIONS
D
0b
D
1a
V
EES
D
1b
D
0a
Q
a
Q
a
11 10 9 8 7 6 5
S
0
S
1
V
EE
V
EES
MR
E
1
E
2
12
13
14
15
16
17
18
19 20 21 22 23 24 25
D
0c
D
1c
D
0d
D
1d
Q
d
4
3
Top View
PLCC
J28-1
2
1
28
27
26
Q
b
Q
b
V
CCA
V
CC
V
CC
Q
c
Q
c
E
1
MR
V
EE
Q
d
E
2
S
1
V
EES
D
0c
D
1c
D
0d
D
1d
Q
d
Q
d
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
S
0
D
1b
D
0b
D
1a
D
0a
Q
a
Q
a
13
7 8 9 10 11 12
Q
c
Q
c
D
1d
E
E
1
E
2
MR
CD
Q
d
V
CC
V
CCA
Rev.: G
Q
b
Q
b
Amendment: /0
D
Q
Q
d
1
Issue Date: July, 1999

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