Max. transparent propagation delay of 900ps
Min. Master Reset and Enable pulse widths of 100ps
min. of 鈥?8mA
鈩?/div>
input pull-down resistors
s
More than 40% faster than Fairchild
s
Approximately 30% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S350 offers six high-speed D-Latches with
both true and complement outputs, and is performance
compatible for use with high-performance ECL systems.
When both enable signals (E
a
and E
b
) are at a logic LOW,
the latches are transparent and the input signals( D
0
鈥揇
5
)
appear at the outputs (Q
0
鈥換
5
) after a propagation delay. If
either or both of the enable signals are at a logic HIGH, then
the latches store the last valid data present on its inputs
before E
a
or E
b
went to a logic HIGH. The Master Reset
(MR) overrides all other input signals and takes the outputs
to a logic LOW state. All inputs have 75K鈩?pull-down
resistors.
PIN CONFIGURATIONS
D
0
Q
0
V
EES
Q
0
Q
1
Q
1
4
3
2
1
28
27
26
19 20 21 22 23 24 25
11 10 9 8 7 6 5
D
2
12
13
14
15
16
17
18
Q
2
Q
2
V
CCA
V
CC
V
CC
Q
3
Q
3
D
3
V
EE
V
EES
MR
E
a
E
b
BLOCK DIAGRAM
D
5
E
b
E
a
MR
D
4
D
E
R
Q
5
Q
5
D
1
Top View
PLCC
J28-1
D
5
Q
5
Q
5
Q
4
D
4
V
EES
Q
4
E
a
MR
V
EE
E
b
D
3
D
E
R
Q
4
Q
4
D
3
D
E
R
Q
3
Q
3
D
4
D
5
Q
5
Q
5
Q
4
Q
4
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
D
2
D
1
D
0
Q
0
Q
0
Q
1
Q
1
D
2
D
E
R
Q
2
Q
2
13
7 8 9 10 11 12
Q
3
V
CC
V
CCA
Q
3
Q
2
Q
2
D
1
D
E
R
Q
1
Q
1
D
0
D
E
R
Q
0
Q
0
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
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2
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