Max. shift frequency of 700MHz
Clock to Q delay max. of 1100ps
min. of 鈥?70mA
鈩?/div>
input pull-down resistors
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
50% faster than Fairchild 300K at lower power
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S336A is functionally the same as the
SY100S336, but has S
n
to TC speed and Sn set-up and
hold times significantly improved, allowing for higher clock
frequency when used as a cascaded multi-stage counter.
The SY100S336A functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
provided. The CET input also functions as the Serial Data
input (S
0
) for a shift-up operation, while the D
3
input serves
as the Serial Data input for the shift-down operation.
When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q
3
output.
The flexiblity provided by the TC/Q
3
output and the D
0
/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (P
n
) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75K鈩?pull-
down resistors.
PIN CONFIGURATIONS
P
2
P
3
V
EES
Q
3
Q
3
D
3
P
1
11 10 9 8 7 6 5
P
0
CP
V
EE
V
EES
MR
S
0
S
1
12
13
14
15
16
17
18
19 20 21 22 23 24 25
CEP
D
0
/CET
V
EES
Top View
PLCC
J28-1
4
3
2
1
28
27
26
Q
2
Q
2
V
CCA
V
CC
V
CC
Q
1
Q
1
PIN NAMES
Pin
Function
Clock Pulse Input
Count Enable Parallel Input (Active LOW)
Serial Data Input/Count Enable Trickle
Input (Active LOW)
Select Inputs
Master Reset Input
V
EE
Substrate
V
CCO
for ECL Outputs
Preset Inputs
Serial Data Input
Terminal Count Output
Data Outputs
Complementary Data Outputs
S
0
MR
V
EE
TC
Q
0
Q
0
S
2
CP
P
0
S
1
CP
CEP
S
2
CEP
D
0
/CET
TC
Q
0
Q
0
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
D
0
/CET
P
1
P
2
P
3
D
3
Q
3
Q
3
S
0
鈥?S
2
MR
V
EES
V
CCA
P
0
鈥?P
3
D
3
TC
Q
0
鈥?Q
3
Q
0
鈥?Q
3
13
7 8 9 10 11 12
Q
1
V
CC
V
CCA
Q
1
Q
2
Q
2
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
MICREL
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