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SY100S331FC Datasheet

  • SY100S331FC

  • TRIPLE D FLIP-FLOP

  • 7頁

  • MICREL   MICREL

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TRIPLE D
FLIP-FLOP
SY100S331
FEATURES
s
Max. toggle frequency of 800MHz
s
Differential outputs
s
I
EE
min. of 鈥?0mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
150% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CP
c
), as well as
its own clock pulse (CP
n
). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CP
c
and CP
n
are LOW and enters the slave on the rising edge
of either CP
c
or CP
n
(or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SD
n
) and Direct Clear (CD
n
) signals. The MR,
MS, SD
n
and DC
n
signals override the clock signals. The
inputs on this device have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
SD
0
CD
0
CP
0
V
EES
D
0
Q
0
Q
0
BLOCK DIAGRAM
CD
2
CP
C
CP
2
D
2
SD
2
CD
1
CP
1
D
1
SD
1
CD
0
CP
0
D
0
SD
0
C
D
CP
D
S
D
Q
2
Q
2
MS
CP
C
V
EE
V
EES
MR
SD
1
D
1
12
13
14
15
16
17
18
11 10 9 8 7 6 5
4
3
Top View
PLCC
J28-1
2
1
28
27
26
19 20 21 22 23 24 25
CD
1
SD
2
V
EES
Q
1
Q
1
V
CCA
V
CC
V
CC
Q
2
Q
2
CP
D
S
D
Q
1
Q
1
CD
2
CP
2
D
2
CP
1
CP
1
C
D
CP
D
S
D
Q
0
Q
0
CD
1
SD
2
CD
2
CP
2
D
2
1
2
3
4
5
6
24 23 22 21 20 19
18
17
Top View
16
Flatpack
15
F24-1
14
13
7 8 9 10 11 12
Q
2
Q
2
V
CC
V
CCA
Q
1
Q
1
MS
D
1
C
D
SD
1
MR
V
EE
CP
C
SD
0
CD
0
CP
0
D
0
Q
0
Q
0
MS MR
Rev.: G
Amendment: /0
1
Issue Date: July, 1999

SY100S331FC 產(chǎn)品屬性

  • 15

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 100S

  • 主復(fù)位

  • D 型總線

  • 差分

  • 3

  • 1

  • 800MHz

  • 300ps

  • 正邊沿

  • -

  • 4.2 V ~ 5.5 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 24-CQFlatpack，Cerpack

  • 管件

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