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SY100S325JCTR Datasheet

  • SY100S325JCTR

  • LOW-POWER HEX ECL-to-TTL TRANSLATOR

  • 103.86KB

  • 5頁

  • MICREL   MICREL

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LOW-POWER HEX
ECL-to-TTL
TRANSLATOR
FEATURES
s
Max. propagation delay of 3.7ns
s
I
EE
min. of 鈥?7mA
s
TTL outputs
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
25% faster than National's 325
s
Differential inputs with built-in offset
s
Voltage and temperature compensation for improved
noise immunity
s
V
BB
output for single-ended use
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S325
DESCRIPTION
The SY100S325 are hex translators for converting
100K ECL logic levels to TTL logic levels. Inputs can be
used as inverting, non-inverting or differential receivers.
An internal reference voltage generator provides V
BB
for
single-ended operation or for use in Schmitt trigger
applications. All inputs have 75K鈩?pull-down resistors.
The outputs will go LOW when the inputs are either open
or have the same potential.
When used in single-ended operation, the apparent
input threshold of the true inputs is 20mV to 40mV higher
(positive) than the threshold of the complementary inputs.
The V
TTL
and V
EE
power may be applied in either order.
PIN CONFIGURATIONS
Q
3
Q
4
Q
5
V
EES
D
5
V
TTL
V
TTL
V
CC
V
CC
V
CC
Q
2
Q
1
25 24 23 22 21 20 19
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
D
5
D
4
D
4
D
3
D
3
V
EES
V
EE
V
BB
D
2
BLOCK DIAGRAM
V
BB
D
0
D
0
D
1
D
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
Q
0
Top View
PLCC
J28-1
15
14
13
12
V
EE
V
BB
D
4
D
3
V
EES
Q
0
D
0
D
1
D
1
D
0
D
2
24
23
D
3
22
21
20 19
18
17
Q
1
D
4
D
5
D
5
D
2
1
2
3
4
5
6
7
8
9
10
11
12
D
2
D
1
D
1
D
0
D
0
Q
0
Q
2
Q
5
Q
4
Q
3
Top View
Flatpack
F24-1
16
15
14
13
Q
3
V
TTL
V
CC
Q
2
Q
4
Q
5
PIN NAMES
Pin
D
0
鈥揇
5
D
0
鈥揇
5
Q
0
鈥換
5
V
EES
V
TTL
V
CCA
Data Inputs
Inverting Data Inputs
Data Outputs
V
EE
Substrate
TTL V
CC
Power Supply
V
CCO
for ECL Outputs
Rev.: F
Amendment: /0
Function
1
V
TTL
V
CC
Issue Date: July, 1999
Q
1

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