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SY100S317JCTR Datasheet

  • SY100S317JCTR

  • TRIPLE 2-WIDE OA/OAI GATE

  • 99.10KB

  • 5頁

  • MICREL   MICREL

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TRIPLE 2-WIDE
OA/OAI GATE
SY100S317
FEATURES
s
Max. propagation delay of 900ps
s
I
EE
min. of 鈥?8mA
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Approximately 40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S317 is a set of ultra-fast, triple 2-wide OR/
AND gates designed for use in high-performance ECL
systems. This device offers both true and complement
outputs. The inputs on this device have 75K鈩?pull-down
resistors.
PIN CONFIGURATIONS
V
EES
D
1a
D
3a
D
2a
D
4a
O
a
O
a
4
3
2
1
28
27
26
19 20 21 22 23 24 25
11 10 9 8 7 6 5
E
a
E
b
V
EE
V
EES
E
c
12
13
14
15
16
17
18
O
b
O
b
V
CCA
V
CC
V
CC
O
c
O
c
Top View
PLCC
J28-1
BLOCK DIAGRAM
E
a
D
1b
D
2b
D
1c
V
EES
D
3b
D
4b
D
1a
D
2a
D
3a
D
4a
E
b
D
1b
D
2b
D
3b
D
4b
E
c
D
1c
D
2c
D
3c
D
4c
O
c
O
c
O
b
O
b
O
a
O
a
D
2c
D
3c
D
4c
D
4b
E
c
V
EE
D
3b
E
b
D
3b
D
4b
D
1c
D
2c
D
3c
D
4c
24 23 22 21 20 19
18
1
2
3
4
5
6
7
Top View
Flatpack
F24-1
17
16
15
14
E
a
D
4a
D
3a
D
2a
D
1a
O
a
O
a
13
8 9 10 11 12
O
c
V
CC
V
CCA
O
c
PIN NAMES
Pin
D
na
鈥?D
nc
E
a
鈥?E
c
O
a
鈥?O
c
O
a
鈥?O
c
V
EES
V
CCA
Function
Data Inputs (n = 1...4)
Enable Inputs
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
O
b
O
b

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