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SY100S307JCTR Datasheet

  • SY100S307JCTR

  • QUINT EXCLUSIVE OR/NOR GATE

  • 100.86KB

  • 5頁(yè)

  • MICREL   MICREL

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QUINT EXCLUSIVE
OR/NOR GATE
FEATURES
s
Max. propagation delay of 1000ps
s
I
EE
min. of 鈥?8mA
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
50% faster than Fairchild 300K at lower power
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
D
1b
D
2b
V
EE
V
EES
D
1c
D
2c
12
13
14
15
16
17
18
19 20 21 22 23 24 25
Top View
PLCC
J28-1
SY100S307
DESCRIPTION
The SY100S307 is an ultra-fast quint exclusive-OR/
NOR gate designed for use in high-performance ECL
systems. A function output that is the wire-OR result of the
exclusive-OR outputs is also available. The inputs on the
device have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
D
1a
O
a
V
EES
D
2a
O
a
O
b
O
b
4
3
2
1
28
27
26
11 10 9 8 7 6 5
O
c
O
c
V
CCA
V
CC
V
CC
F
O
d
BLOCK DIAGRAM
F
D
1a
D
2a
D
1b
D
2b
D
1c
D
2c
D
1d
D
2d
D
1e
D
2e
O
a
O
a
O
b
O
b
O
c
O
c
O
d
O
d
O
e
O
e
D
2d
D
1e
D
2e
V
EES
O
e
O
e
D
1d
O
d
D
2d
D
2c
D
1c
V
EE
D
2b
1
2
3
4
5
6
D
1d
D
1e
D
2e
O
e
O
e
O
d
24 23 22 21 20 19
18
17
Top View
16
Flatpack
15
F24-1
14
13
7 8 9 10 11 12
D
1b
D
2a
D
1a
O
a
O
a
O
b
O
b
F
V
CC
V
CCA
PIN NAMES
Pin
D
na
鈥?D
ne
E
O
a
鈥?O
e
O
a
鈥?O
e
V
EES
V
CCA
Function
Data Inputs (n-1...5)
Enable Input
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
O
d
Rev.: G
O
c
O
c
Amendment: /0
1
Issue Date: July, 1999

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