Max. propagation delay of 700ps
min. of 鈥?5mA
鈩?/div>
input pull-down resistors
s
50% faster than Fairchild 300K
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
D
1b
D
2b
V
EE
V
EES
E
D
1c
D
2c
12
13
14
15
16
17
18
Top View
PLCC
J28-1
SY100S302
DESCRIPTION
The SY100S302 offers five 2-input OR/NOR gates
designed for use in high-performance ECL systems. The
five gates are controlled by a common Enable signal. All
inputs have 75K鈩?pull-down resistors and all outputs are
buffered.
PIN CONFIGURATIONS
D
1a
O
a
V
EES
D
2a
O
a
O
b
O
b
11 10 9 8 7 6 5
4
3
2
1
28
27
26
O
c
O
c
V
CCA
V
CC
V
CC
O
d
O
d
BLOCK DIAGRAM
19 20 21 22 23 24 25
D
2d
D
1e
V
EES
D
2e
O
e
O
e
D
1d
D
1c
E
V
EE
D
2b
D
1a
D
2a
D
1b
D
2b
D
1c
D
2c
D
1d
D
2d
D
1e
D
2e
O
a
O
a
O
b
O
b
O
c
O
c
O
d
V
CC
V
CCA
D
1d
D
2d
D
1e
D
2e
O
e
O
e
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
D
1b
D
2c
D
2a
D
1a
O
a
O
a
O
b
O
b
13
7 8 9 10 11 12
O
d
O
c
O
c
O
d
O
d
O
e
O
e
Pin
PIN NAMES
Function
Data Inputs (n-1...5)
Enable Input
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
E
D
na
鈥?D
ne
E
O
a
鈥?O
e
O
a
鈥?O
e
V
EES
V
CCA
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
1
2
3
4
5
