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SY100S301JCTR Datasheet

  • SY100S301JCTR

  • TRIPLE 5-INPUT OR/NOR GATE

  • 5頁

  • MICREL   MICREL

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TRIPLE 5-INPUT
OR/NOR GATE
SY100S301
FEATURES
s
Max. propagation delay of 750ps
s
I
EE
min. of 鈥?5mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for
improved noise immunity
s
20% faster than Fairchild 300K at lower power
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S301 is an ultra-fast triple 5-input OR/NOR
gate designed for use in high-performance ECL systems.
The inputs on this device have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
V
EES
D
1a
D
4a
D
3a
D
2a
O
a
O
a
4
Top View
PLCC
J28-1
3
2
1
28
27
26
19 20 21 22 23 24 25
11 10 9 8 7 6 5
D
5a
D
1b
V
EE
V
EES
D
2b
D
3b
D
4b
12
13
14
15
16
17
18
O
b
O
b
V
CCA
V
CC
V
CC
O
c
O
c
BLOCK DIAGRAM
D
1a
D
2a
D
3a
D
4a
D
5a
O
a
O
a
D
1c
D
2c
V
EES
D
5b
D
3c
D
4c
D
5c
D
3b
D
2b
V
EE
D
1b
D
4b
D
5b
D
1c
D
2c
D
3c
D
4c
D
5c
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
D
5a
D
4a
D
3a
D
2a
D
1a
O
a
O
a
D
5b
D
1c
D
2c
D
3c
D
4c
D
5c
O
c
O
c
PIN NAMES
Pin
D
na
, D
nb
, D
nc
O
a
, O
b
, O
c
O
a
, O
b
, O
c
V
EES
V
CCA
Function
Data Inputs (n-1...5)
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
O
c
V
CC
V
CCA
O
b
O
b
Rev.: F
Amendment: /0
Issue Date: July, 1999
D
1b
D
2b
D
3b
D
4b
O
b
O
b
13
7 8 9 10 11 12
1
O
c

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