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SY100HA643
DESCRIPTION
The SY100HA643 is an enhanced dual supply, low skew
translating 1:8 clock driver. Devices in the Micrel-Synergy
H600 translators series utilize the 28-lead PLCC for optimal
power pinning, signal flow through and electrical
performance. The dual-supply HA643 is similar to the H641,
which is a single-supply 1:9 version of the same function,
with higher performance than the H643 versions.
The device features a 48mA TTL output stage, with AC
performance specified into a 20pF load capacitance. A
Latch is provided on-chip. When LEN is LOW (or left open,
in which case it is pulled LOW by the internal pulldowns)
the latch is transparent. A HIGH on the enable pin (EN)
forces all outputs LOW.
The 100HA643 is compatible with 100K ECL logic levels.
PIN CONFIGURATION
OGND
3
Q
5
OVT
2
Q
6
OGND
4
Q
4
Q
7
18
17
BLOCK DIAGRAM
Q
0
25 24
23 22 21 20 19
Q
3
OGND
2
26
27
28
1
2
3
4
5
6
7
8
9
10 11
IVT
2
IGND
2
V
CCE
V
CCE
LEN
V
BB
D
Q
1
Q
2
OVT
1
Q
1
OGND
1
Q
0
SY100HA643
TOP VIEW
PLCC
16
15
14
13
12
Q
2
1GND
1
V
EE
IVT
1
Q
3
D
D
V
BB
LEN
EN
D
TTL OUTPUTS
Q
PIN NAMES
Pin
Function
TTL Output Ground (0V)
Output V
CC
(+5.0V)
Internal TTL GND (0V)
Internal TTL V
CC
(+5.0V)
ECL V
EE
(-5.2/-4.5V)
ECL Ground (0V)
Signal Input (ECL)
V
BB
Reference Output
Signal Outputs (TTL)
Enable Input (ECL)
Latch Enable Input (ECL)
Rev.: G
Amendment: /1
Issue Date: August, 1998
Q
4
OGND
OVTTTL
IGND
Q
5
IVT
V
EE
Q
6
V
CCE
D, D
V
BB
Q
7
Q0 - Q7
EN
LEN
1
V
EE
V
EE
EN
D