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SY10H641
SY100H641
FEATURES
s
Input frequencies up to 135MHz
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PECL-to-TTL version of popular ECLinPS E111
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Guaranteed low skew specification
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Latched input
s
Differential internal design
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V
BB
output VECL for single-ended operation
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Single +5V supply
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Reset/enable
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Extra TTL and ECL power/ground pins
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Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
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Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H641 are single supply, low skew
translating 1:9 clock drivers. Devices in the Micrel-
Synergy H600 translator series utilize the 28-lead PLCC
for optimal power pinning, signal flow-through and
electrical performance.
The devices feature a 24mA TTL output stage with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled LOW by the internal pull-
downs), the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
TTL Outputs
Q0
PIN CONFIGURATION
G
T
Q
6
V
T
Q
7
V
T
Q
8
G
T
25 24 23 22 21 20 19
G
T
Q
5
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
V
BB
D
D
V
E
LEN
G
E
EN
Q1
V
T
Q
4
V
T
Q
3
G
T
TOP VIEW
PLCC
15
14
13
12
Q2
G
T
Q
2
V
T
Q
1
V
T
Q
0
D
D
V
BB
D
Q
Q4
PIN NAMES
Q5
Pin
G
T
Q6
V
T
V
E
G
E
Q7
D, D
V
BB
Q
0
- Q
8
Q8
EN
LEN
Function
TTL Ground (0V)
TTL V
CC
(+5.0V)
ECL V
CC
(+5.0V)
ECL Ground (0V)
Signal Input (PECL)
V
BB
Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input (PECL)
Rev.: D
Amendment: /0
LEN
EN
1
G
T
Issue Date: March, 1999
PECL Input
Q3
1
2
3
4
5
