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SY100ELT25ZCTR Datasheet

  • SY100ELT25ZCTR

  • DIFFERENTIAL ECL-to-TTL TRANSLATOR

  • 5頁

  • MICREL   MICREL

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DIFFERENTIAL
ECL-to-TTL
TRANSLATOR
FEATURES
s
2.6ns typical propagation delay
s
Differential ECL inputs
s
24mA TTL outputs
s
Flow-through pinouts
s
Available in 8-pin SOIC package
SY100ELT25
DESCRIPTION
The SY100ELT25 is a differential ECL-to-TTL
translator. Because ECL levels are used, a +5V, 鈥?.2V
(or 鈥?.5V) and ground are required. The small outline 8-
lead SOIC package and the single gate of the ELT25
makes it ideal for those applications where performance,
space and low power are at a premium.
The V
BB
output allows the ELT25 to also be used in a
single-ended input mode. In this mode the V
BB
output is
tied to the D input for a non-inverting buffer or the D
input for an inverting buffer. If used the V
BB
pin should
be bypassed to ground via a 0.01碌F capacitor.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Q
TTL Output
Differential ECL Inputs
Positive Supply
Negative Supply
Reference Output
Ground
Function
V
EE
D
D
V
BB
1
2
3
4
8
7
6
5
V
CC
Q
NC
GND
D
V
CC
V
EE
V
BB
GND
SOIC
TOP VIEW
Rev.: A
Amendment: /0
1
Issue Date: October 1999

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