5V/3.3V TRIPLE ECL/LVECL-TO-
PECL/LVPECL TRANSLATOR
SY100EL90V
FEATURES
s
3.3V and 5V power supply options
s
500ps propagation delay
s
Fully differential design
s
Supports both standard and low voltage operation
s
Available in 20-pin SOIC package
DESCRIPTION
The SY100EL90V is a triple ECL/LVECL-to-PECL/
LVPECL translator. The device can translate over all
combinations of supply voltages: -5V ECL to 5V PECL,
-5V ECL to 3.3V LVPECL, -3.3V LVECL to 5V PECL or
-3.3V LVECL to 3.3V LVPECL.
A V
BB
output is provided for interfacing with single
ended ECL signals at the input. If a single ended input is
to be used, the V
BB
output should be connected to the D
input. The active signal would then drive the D input.
When used, the V
BB
output should be bypassed to via a
0.01碌F capacitor. The V
BB
output is designed to act as
the switching reference for the EL90V under single ended
input switching conditions. As a result this pin can only
source/sink up to 0.5mA of current.
To accomplish the level translation the EL90V requires
three power rails. The V
CC
supply should be connected
to the positive supply, and the V
EE
pin should be
connected to the negative power supply. The GND pins
as expected are connected to the system ground plane.
Both V
EE
and V
CC
should be bypassed to ground via
0.01碌F capacitors.
Under open input conditions, the D input will be biased
at V
CC
/2 and the D input will be pulled to V
EE
. This
condition will force the Q output to a LOW, ensuring
stability.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
1
ECL
20
V
CC
19
18
17
16
15
14
13
12
11
PECL
D
0
2
D
0
3
V
BB
4
ECL
PECL
Q
0
Q
0
GND
Q
1
Q
1
GND
Q
2
Q
2
V
CC
D
1
5
D
1
6
V
BB
7
PIN NAMES
Pin
Dn
Q
n
V
BB
Function
ECL/LVECL Inputs
PECL/LVPECL Outputs
ECL/LVECL Reference Voltage Output
PECL
ECL
D
2
8
D
2
9
V
EE
10
SOIC
TOP VIEW
FUNCTION TABLE
Function
鈥?V ECL to 5V PECL
鈥?V ECL to 3.3V LVPECL
鈥?.3V LVECL to 5V PECL
鈥?.3V LVECL to 3.3V LVPECL
V
CC
5V
3.3V
5V
3.3V
GND
0V
0V
0V
0V
V
EE
鈥?V
鈥?V
鈥?.3V
鈥?.3V
Rev.: F
Amendment: /1
October, 1998
1
Isse Date:
MICREL
1
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