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Input Line Receiver
D Flip-Flop
Bias Control Circuitry
Output Current Switch
PIN CONFIGURATION
NC
CLK
CLK
R
SET
V
CCO
D
D
MR
1
2
3
4
5
6
7
8
16
15
14
V
CC
NC
MC
OUT
OUT
V
BB
NC
V
EE
Top View
SOIC
Z16-2
13
12
11
10
9
A logic HIGH level at the data input results in the
modulation current flowing through the OUT pin on the
next rising edge of the clock. A logic HIGH level at the
master reset input will disable the modulation current.
The device incorporates complementary open collector
outputs with a capability of driving peak current of 75
mA.
The laser driver current is adjustable by selection of
R
SET
. The resistor R
EXT
must be placed between OUT
and V
CC
to dissipate the worst case power. R
SER
is
recommended to fix laser diode matching issues.
The SY100EL1001 utilizes the high performance
bipolar ASSET technology.
BLOCK DIAGRAM
V
CC
R
EXT
V
BB
OUT
OUT
R
SER
D, D
CLK, CLK
MR
D Flip-Flop
to Laser Diode
BIAS
Control
Modulation Control
MC
R
SET
V
EE
Rev.: E
Amendment: /0
1
Issue Date: August, 1998