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SY100E451JCTR Datasheet

  • SY100E451JCTR

  • 6-BIT REGISTER DIFFERENTIAL DATA CLOCK

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6-BIT REGISTER
DIFFERENTIAL DATA CLOCK
SY10E451
SY100E451
FEATURES
s
1100MHz min. toggle frequency
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
Differential inputs: data and clock
s
V
BB
output for single-ended use
s
Asynchronous Master Reset
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E451
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E451 offer six D-type flip-flops with single-
ended outputs and differential data and clock inputs,
designed for use in new, high-performance ECL systems.
The registers are triggered by the rising edge of the CLK
input.
A logic HIGH on the Master Reset (MR) input resets all
outputs to a logic LOW. The V
BB
output is provided for use
as a reference voltage for single-ended reception of ECL
signals to that device only. When used for this purpose, it
is recommended that V
BB
is decoupled to V
CC
via a 0.01碌F
capacitor.
BLOCK DIAGRAM
D
0
D
0
PIN CONFIGURATION
D
3
V
CCO
18
17
D
5
D
5
D
4
D
R
Q
0
25 24 23 22 21 20 19
D
1
D
1
D
R
Q
1
CLK
V
BB
CLK
V
EE
D
4
D
3
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
5
Q
4
V
CC
Q
3
V
CCO
Q
2
Q
1
D
2
D
2
D
R
Q
2
D
3
D
3
MR
NC
D
0
TOP VIEW
PLCC
J28-1
16
15
14
13
12
D
R
Q
3
V
CCO
D
1
D
2
D
4
D
4
D
R
Q
4
D
5
D
5
CLK
CLK
MR
V
BB
D
R
Q
5
PIN NAMES
Pin
D
0
鈥揇
5
D
0
鈥揇
5
CLK
CLK
MR
V
BB
Q
0
鈥換
5
V
CCO
Function
+ Data Input
鈥?Data Input
+ Clock Input
鈥?Clock Input
Master Reset Input
V
BB
Output
Data Outputs
V
CC
to Output
Q
0
Rev.: C
D
0
D
1
D
2
Amendment: /1
1
Issue Date: February, 1998

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