3-BIT DIFFERENTIAL
FLIP-FLOP
SY10E431
SY100E431
FEATURES
s
Differential D, clock and Q
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
V
BB
output for single-ended use
s
1100MHz min. toggle frequency
s
Edge-triggered asynchronous set and reset
s
Fully compatible with Motorola MC10E/100E431
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E431 are 3-bit flip-flops with differential
clock, data input and data output.
The asynchronous Set and Reset controls are edge-
triggered rather than level controlled. This allows the user
to rapidly set or reset the flip-flop and then continue
clocking at the next clock edge without the necessity of
de-asserting the set/reset signal (as would be the case
with a level controlled set/reset).
The E431 is also designed with larger internal swings,
an approach intended to minimize the time spent crossing
the threshold region and thus reduces the metastability
susceptibility window.
BLOCK DIAGRAM
S
0
D
0
D
0
CLK
0
CLK
0
R
0
S
1
D
1
D
1
CLK
1
CLK
1
R
1
S
2
D
S
Q
Q
R
Q
1
Q
1
D
S
Q
Q
R
Q
0
PIN CONFIGURATION
CLK
2
CLK
2
D
2
V
BB
D
2
R
2
Q
0
25 24 23 22 21 20 19
CLK
1
CLK
1
R
1
V
EE
S
1
D
1
D
1
S
2
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
TOP VIEW
PLCC
J28-1
16
15
14
13
12
Q
2
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
CLK
0
CLK
0
D
0
D
0
D
2
D
2
CLK
2
CLK
2
R
2
V
BB
D
S
Q
Q
Q
2
Q
2
R
PIN NAMES
Pin
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
R
n
L
L
Z
L
S
n
L
L
L
Z
Q
n
L
H
L
H
S[0:2]
R[0:2]
V
BB
Q[0:2], Q[0:2]
V
CCO
Function
Differential Data Inputs
Differential Clock Inputs
Edge Triggered Set Inputs
Edge Triggered Reset Inputs
V
BB
Reference Output
Differential Data Outputs
V
CC
to Output
TRUTH
D
n
L
H
X
X
TABLE
(1)
CLK
n
Z
Z
L
L
NOTE:
1. Z = LOW-to-HIGH transition.
Rev.: C
Amendment: /1
1
V
CCO
Issue Date: February, 1998
R
0
S
0
1
2
3
4
