QUINT LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
FEATURES
s
3.3V and 5V power supplies required
s
Also, supports LVPECL-to-PECL translation
s
500ps propagation delays
s
Fully differential design
s
Differential line receiver capability
s
Available in 28-pin PLCC package
SY100E417
DESCRIPTION
The SY100E417 is a quint LVPECL-to-PECL translator.
It can also be used as a quint PECL-to-LVPECL translator.
The device receives standard PECL signals and translates
them to differential LVPECL output signals (or vice versa).
The SY100E417 can also be used as a differential line
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.
However, please note that for the latter we will need two
different power supplies. Please refer to Function Table for
more details.
A V
BB
output is provided for interfacing single ended
input signals. If a single ended input is to be used, the V
BB
output should be connected to the Dn input and the active
signal will drive the Dn input. When used, the V
BB
should
be bypassed to V
CC
via a 0.01碌F capacitor. The V
BB
is
designed to act as a switching reference for the SY100E417
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100E417 requires three power rails. The V
CC
and
V
CC
_V
BB
supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the V
CCO
supply, and GND is connected to the system ground plane.
Both the V
CC
and V
CCO
should be bypassed to ground with
a 0.01碌F capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100E417 requires three power rails as well. The 5.0V
supply is connected to the V
CC
and V
CCO
pins, 3.3V supply
is connected to the V
CC
_V
BB
pin and GND is connected to
the system ground plane. V
CC
_V
BB
is used to provide a
proper V
BB
output level if a single ended input is used.
V
CC
_V
BB
= 3.3V is only required for single-ended LVPECL
input. For differential LVPECL input, V
CC
_V
BB
can be either
3.3V or 5.0V.
Under open input conditions, the Dn input will be biased
at a V
CC
/2 voltage level and the Dn input will be pulled to
GND. This condition will force the "Qn" output low, ensuring
stability.
BLOCK DIAGRAM
D
0
D
0
D
1
D
1
D
2
D
2
D
3
D
3
D
4
D
4
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
FUNCTION TABLE
Function
PECL-to-LVPECL
LVPECL-to-PECL
PECL-to-PECL
LVPECL-to-LVPECL
Vcc
5.0V
5.0V
5.0V
5.0V
Vcco
3.3V
5.0V
5.0V
3.3V
Vcc_V
BB
5.0V
3.3V
5.0V
3.3V
Rev.: B
Amendment: /1
1
Issue Date: March, 1999
MICREL
1
2
3
4
5
