850ps max. propagation delay
鈩?/div>
input pulldown resistors
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Fully compatible with Motorola MC10E/100E163
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E163 offer two 8:1 multiplexers designed
for use in new, high-performance ECL systems. The E163
has differential outputs and common select inputs. The
select inputs (SEL
0
, SEL
1
, SEL
2
) determine which one of
the eight data inputs (A
0
鈥揂
7
, B
0
鈥揃
7
) is propagated to the
output.
BLOCK DIAGRAM
A
0
PIN CONFIGURATION
B
7
V
CCO
B
2
B
3
B
4
B
5
A
1
A
2
A
3
QA
QA
25 24 23 22 21 20 19
B
1
B
0
SEL
0
V
EE
SEL
1
SEL
2
A
0
B
6
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
QB
QB
V
CC
NC
V
CCO
QA
QA
A
4
A
5
A
6
A
7
SEL
0
SEL
1
SEL
2
PLCC
TOP VIEW
J28-1
16
15
14
13
12
A
1
A
2
A
3
A
4
TO SIDE B
PIN NAMES
Pin
A
0
鈥揂
7
B
0
鈥揃
7
SEL
0, 1, 2
QA, QB
QA, QB
V
CCO
Function
A Data Inputs (D)
B Data Inputs (D)
Select Inputs
True Outputs
Inverting Outputs
V
CC
to Output
A
6
A
7
Rev.: C
A
5
Amendment: /1
1
Issue Date: February, 1998