(on) = 2.1鈩?/div>
EXTREMELY HIGH dv/dt CAPABILITY
GATE-TO-SOURCE ZENER DIODES
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
TO-247
DESCRIPTION
The third generation of MESH OVERLAY鈩?Power
MOSFETs for very high voltage exhibits unsur-
passed on-resistance per unit area while integrating
back-to-back Zener diodes between gate and
source. Such arrangement gives extra ESD capabil-
ity with higher ruggedness performance as request-
ed by a large variety of single-switch applications.
APPLICATIONS
s
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s
WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(1)
P
TOT
I
GS
V
ESD(G-S)
dv/dt
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Gate-source Current (*)
Gate source ESD(HBM-C=100pF, R=15K鈩?
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
900
900
鹵25
5.2
3.3
21
160
1.52
鹵50
4
3
鈥?5 to 150
150
(*) Limited by maximum temperature allowed
Unit
V
V
V
A
A
A
W
W/擄C
mA
KV
V/ns
擄C
擄C
(鈥?Pulse width limited by safe operating area
(1)I
SD
鈮?.2A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
October 2000
1/8
next