鈻?/div>
16/32-bit 96 MHz ARM9E based MCU
鈥?ARM966E-S RISC core: Harvard archi-
tecture, 5-stage pipeline, Tightly-Coupled
Memories (SRAM and Flash)
鈥?STR91xF implementation of core adds high-
speed burst Flash memory interface,
instruction prefetch queue, branch cache
鈥?Up to 96 MIPS directly from Flash memory
鈥?Single-cycle DSP instructions are supported
鈥?Binary compatible with 16/32-bit ARM7 code
鈻?/div>
Dual burst Flash memories, 32-bits wide
鈥?256KB/512KB Main Flash, 32KB 2nd Flash
鈥?Sequential Burst operation up to 96 MHz
鈥?100K min erase cycles, 20 yr min retention
鈻?/div>
SRAM, 32-bits wide
鈥?64K or 96K bytes, optional battery backup
鈻?/div>
9 programmable DMA channels
鈥?One for Ethernet, eight programmable chnls
鈻?/div>
Clock, reset, and supply management
鈥?Two supplies required. Core: 1.8V +/-10%,
I/O: 2.7 to 3.6V
鈥?Internal osc operating with ext. 4-25MHz xtal
鈥?Internal PLL up to 96MHz
鈥?Real-time clock provides calendar functions,
tamper detection, and wake-up functions
鈥?Reset Supervisor monitors voltage supplies,
watchdog timer, wake-up unit, ext. reset
鈥?Brown-out monitor for early warning interrupt
鈥?Run, Idle, and Sleep Mode as low as 50 uA
鈻?/div>
Operating temperature -40 to +85擄C
鈻?/div>
LQFP80 12 x12mm
LQFP128 14 x 14mm
鈻?/div>
8-channel, 10-bit A/D converter (ADC)
鈥?0 to 3.6V range, 2 usec conversion time
鈻?/div>
11 Communication interfaces
鈥?10/100 Ethernet MAC with DMA and MII port
鈥?USB Full-speed (12 Mbps) slave device
鈥?CAN interface (2.0B Active)
鈥?3 16550-style UARTs with IrDA protocol
鈥?2 Fast I
2
C鈩? 400 kHz
鈥?2 channels for SPI鈩? SSI鈩? or Microwire鈩?/div>
鈥?8/16-bit EMI bus on 128 pin packages
鈻?/div>
Up to 80 I/O pins (muxed with interfaces)
鈥?5V tolerant, 16 have high sink current (8mA)
鈥?Bit-wise manipulation of pins within a port
鈻?/div>
16-bit standard timers (TIM)
鈥?4 timers each with 2 input capture, 2 output
compare, PWM and pulse count modes
鈻?/div>
3-Phase induction motor controller (IMC)
鈥?3 pairs of PWM outputs, adjustable centers
鈥?Emergency stop, dead-time gen, tach input
鈻?/div>
JTAG interface with boundary scan
鈥?ARM EmbeddedICE廬 RT for debugging
鈥?In-System Programming (ISP) of Flash
鈻?/div>
Embedded trace module (ARM ETM9)
鈥?Hi-speed instruction tracing, 9-pin interface
Vectored interrupt controller (VIC)
鈥?32 IRQ vectors, 30 intr pins, any can be FIQ
鈥?Branch cache minimizes interrupt latency
Device summary
Features
STR910FM32X STR910FW32X STR911FM42X STR911FM44X STR912FW42X STR912FW44X
256+32
64
CAN, EMI,
80 I/Os
LQFP128
256+32
96
512+32
96
256+32
512+32
96
96
Ethernet, USB, CAN, EMI,
80 I/Os
LQFP128
FLASH - Kbytes
256+32
RAM - Kbytes
64
Peripheral
CAN, 48 I/Os
functions
Packages
LQFP80
USB, CAN, 48 I/Os
LQFP80
April 2006
Rev 1
1/72
72
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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