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STP3NA50FI Datasheet

  • STP3NA50FI

  • N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STP3NA50
STP3NA50FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STP3NA50
STP3NA50FI
s
s
s
s
s
s
s
V
DSS
500 V
500 V
R
DS( on)
< 3
鈩?/div>
< 3
鈩?/div>
I
D
3.3 A
2.3 A
TYPICAL R
DS(on)
= 2.4
鈩?/div>
鹵
30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100
o
C
LOW INTRINSIC CAPACITANCES
GATE GHARGE MINIMIZED
REDUCED THRESHOLD VOLTAGE SPREAD
TO-220
3
1
2
1
2
3
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low R
DS(on)
and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Value
STP3NA50
STP3NA50FI
500
500
鹵
30
3.3
2.1
13.2
80
0.64
錚?/div>
-65 to 150
150
2.3
1.5
13.2
40
0.32
2000
o
Unit
V
D S
V
DG R
V
GS
I
D
I
D
I
D M
(鈥?
P
tot
V
ISO
T
stg
T
j
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
G S
= 20 k鈩?
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
Derating Factor
Insulation Withstand Voltage (DC)
Storage Temperature
Max. Operating Junction Temperature
V
V
V
A
A
A
W
W/
o
C
V
o
o
C
C
(鈥? Pulse width limited by safe operating area
November 1996
1/10

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