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STLVD210 Datasheet

  • STLVD210

  • DIFFERENTIAL LVDS CLOCK DRIVER

  • 9頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STLVD210
DIFFERENTIAL LVDS CLOCK DRIVER
s
s
s
s
s
s
s
s
s
100ps PART-TO-PART SKEW
50ps BANK SKEW
DIFFERENTIAL DESIGN
MEETS LVDS SPEC. FOR DRIVER
OUTPUTS AND RECEIVER INPUTS
REFERENCE VOLTAGE AVAILABLE
OUTPUT V
BB
LOW VOLTAGE V
CC
RANGE OF 2.375V TO
2.625V
HIGH SIGNALLING RATE CAPABILITY
(EXCEEDS 700MHz)
SUPPORT OPEN, SHORT, AND
TERMINATED INPUT FAIL-SAFE (LOW
OUTPUT STATE)
PROGRAMMABLE DRIVERS POWER OFF
CONTROL
TQFP32
DESCRIPTION
The STLVD210 is a low skew programmable
1-to-5 dual differential LVDS driver, designed with
clock distribution in mind. The LVDS input signals
can be either differential or single-ended if the
VBB output is used.
The STLVD210 is provided with a 11 bit shift
register with a serial in and a Control Register.
The purpose is to enable or power off each output
clock channel and to select the clock input. The
ORDERING CODES
Type
STLVD210BF
STLVD210BFR
Temperature
Range
-40 to 85 擄C
-40 to 85 擄C
Package
STLVD210 is specifically designed, modelled and
produced with low skew as the key goal. Optimal
design and layout serve to minimize gate to gate
skew within a device. The net result is a
dependable guaranteed low skew device.
The STLVD210 can be used for high performance
clock distribution in 2.5V systems with LVDS
levels. Designers can be take advantage of the
device鈥檚 performance to distribute low skew
clocks across the backplane or the board.
Comments
250 parts per Tray
2400 parts per reel
TQFP32 (Tray)
TQFP32 (Tape & Reel)
December 2002
1/9

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