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STK15C68-P25 Datasheet

  • STK15C68-P25

  • 8K x 8 AutoStore nvSRAM

  • 79.01KB

  • 9頁

  • ETC

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STK15C68
8K x 8
AutoStore鈩?/div>
nvSRAM
High Performance CMOS
Nonvolatile Static RAM
FEATURES
鈥?Nonvolatile Storage Without Battery Problems
鈥?Directly Replaces 8K x 8 static RAM, Battery
Backed RAM or EEPROM
鈥?25ns, 35ns and 45ns Access Times
鈥?Store to EEPROM Initiated by Software or
AutoStore鈩?/div>
on Power Down
鈥?Recall to SRAM by Software or Power Restore
鈥?15mA I
CC
at 200ns Cycle Time
鈥?Unlimited Read, Write and Recall Cycles
鈥?1,000,000 Store Cycles to EEPROM
鈥?100 Year Data Retention Over Full Industrial
Temperature Range
鈥?Commercial and Industrial Temp. Ranges
鈥?28 Pin 600 or 300 mil PDIP and 350 mil SOIC
DESCRIPTION
The STK15C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent, nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
EEPROM (the
STORE
operation) can take place auto-
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the
RECALL
operation) take place automatically on res-
toration of power. Initiation of STORE and RECALL
cycles can also be controlled by entering control
sequences on the SRAM inputs. The nvSRAM can be
used in place of existing 8K x 8 SRAMs and also matches
the pinout of 8k x 8 Battery Backed SRAMs, EPROMs,
and EEPROMs, allowing direct substitution while enhanc-
ing performance. There is no limit on the number of read
or write cycles that can be executed and no support cir-
cuitry is required for microprocessor interface.
BLOCK DIAGRAM
EEPROM ARRAY
128 x 512
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
STORE
STATIC RAM
ARRAY
128 x 512
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
12
A
7
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
POWER
CONTROL
RECALL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
A
12
DQ
1
DQ
2
V
SS
28 - 300 PDIP
28 - 600 PDIP
28 - 350 SOIC
PIN NAMES
A
0
A
1
A
2
A
3
A
4
A
10
G
A
0
- A
12
W
DQ
0
- DQ
7
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
E
W
E
G
V
CC
V
SS
4-61

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