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STK14C88-N25 Datasheet

  • STK14C88-N25

  • 32K x 8 AutoStore nvSRAM QuantumTrap CMOS Nonvolatile Static...

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STK14C88
32K x 8
AutoStore鈩?/div>
nvSRAM
QuantumTrap鈩?/div>
CMOS
Nonvolatile Static RAM
FEATURES
鈥?25ns, 35ns and 45ns Access Times
鈥?鈥淗ands-off鈥?Automatic
STORE
with External
68碌F Capacitor on Power Down
鈥?/div>
STORE
to nonvolatile elements Initiated by
Hardware, Software or
AutoStore鈩?/div>
鈥?/div>
RECALL
to SRAM Initiated by Software or
Power Restore
鈥?10mA Typical I
CC
at 200ns Cycle Time
鈥?Unlimited READ, WRITE and
RECALL
Cycles
鈥?1,000,000
STORE
Cycles to nonvolatile ele-
ments (Commercial/Industrial)
鈥?100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
鈥?Single 5V + 10% Operation
鈥?Commercial, Industrial and Military Tempera-
tures
鈥?32-Pin SOIC, DIP and LCC Packages
DESCRIPTION
The Simtek STK14C88 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the nonvolatile elements.
Data transfers from the
SRAM
to the nonvolatile ele-
ments (the
STORE
operation) can take place auto-
matically on power down. A 68碌F or larger capacitor
tied from V
CAP
to ground guarantees the
STORE
operation, regardless of power-down slew rate or
loss of power from 鈥渉ot swapping鈥? Transfers from
the nonvolatile elements to the
SRAM
(the
RECALL
operation) take place automatically on restoration of
power. Initiation of
STORE
and
RECALL
cycles can
also be software controlled by entering specific read
sequences. A hardware
STORE
may be initiated with
the HSB pin.
BLOCK DIAGRAM
V
CCX
Quantum Trap
512 x 512
V
CAP
PIN CONFIGURATIONS
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
POWER
CONTROL
ROW DECODER
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
V
CCX
HSB
W
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
32 - LCC
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
13
32 - DIP
32 - SOIC
INPUT BUFFERS
PIN NAMES
A
0
- A
14
DQ
0
-DQ
7
E
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
W
G
HSB
V
CCX
V
CAP
V
SS
December 2002
1
Document Control # ML0014 rev 0.0

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