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STK14C88-3WF55I Datasheet

  • STK14C88-3WF55I

  • 32K x 8 AutoStore⑩ nvSRAM QuantumTrap CMOS Nonvolatile Stat...

  • 355.95KB

  • 13頁

  • ETC

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STK14C88-3
32K x 8
AutoStore鈩?/div>
nvSRAM
QuantumTrap鈩?/div>
CMOS
Nonvolatile Static RAM
FEATURES
鈥?35ns, 45ns and 55ns Access Times
鈥?鈥淗ands-off鈥?Automatic
STORE
with External
68碌F Capacitor on Power Down
鈥?/div>
STORE
to nonvolatile elements Initiated by
Hardware, Software or
AutoStore鈩?/div>
鈥?/div>
RECALL
to SRAM Initiated by Software or
Power Restore
鈥?10mA Typical I
CC
at 200ns Cycle Time
鈥?Unlimited READ, WRITE and
RECALL
Cycles
鈥?1,000,000
STORE
Cycles to nonvolatile ele-
ments (Commercial/Industrial)
鈥?100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
鈥?Single 3.3V
+
0.3V Operation
鈥?Commercial and Industrial Temperatures
鈥?32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88-3 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in nonvolatile elements. Data
transfers from the
SRAM
to the nonvolatile elements
(the
STORE
operation) can take place automatically
on power down. A 68碌F or larger capacitor tied from
V
CAP
to ground guarantees the
STORE
operation,
regardless of power-down slew rate or loss of power
from 鈥渉ot swapping鈥? Transfers from the nonvolatile
elements to the
SRAM
(the
RECALL
operation) take
place automatically on restoration of power. Initia-
tion of
STORE
and
RECALL
cycles can also be soft-
ware controlled by entering specific read
sequences. A hardware
STORE
may be initiated with
the HSB pin.
BLOCK DIAGRAM
V
CCX
Quantum Trap
512 x 512
V
CAP
POWER
CONTROL
PIN CONFIGURATIONS
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
13
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
V
CCX
HSB
W
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
ROW DECODER
PIN NAMES
A
0
- A
14
Address
Inputs
DQ
0
-DQ
7
Data In/Out
E
Chip
Enable
W
Write
Enable
G
Output
Enable
HSB
Hardware
Store
Busy (I/O)
V
CCX
Power
(+ 3.3V)
32 - DIP
32 - SOIC
V
CAP
Capacitor
V
SS
Ground
48 - SSOP
(not to scale)
November 2003
1
Document Control # ML0015 rev 0.3

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