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STi5300

High-performance set-top box decoder

DATA BRIEF

DESCRIPTION

The new STi5300 MPEG-2 decoder from ST

provides a step-change in performance for pay TV

set-top boxes and digital video recorders.

Delivering 1.33 GOPS of processing power

through an ST230 VLIW CPU running at 333 MHz,

ST has ensured that manufacturers鈥?investment in

new products is protected as the STi5300 can

easily accommodate today鈥檚 interactive software,

and provides a platform that can support the even

more demanding applications of the future. Both

Linux and OS21 operating systems are supported,

and an MMU provides support for virtual memory

management.

The STi5300鈥檚 power comes from the VLIW

architecture of the ST230 CPU. This allows four

instructions to be executed at each CPU cycle,

dramatically

increasing

performance.

By

maintaining pin compatibility with the STi5100,

manufacturers can make use of the STi5300 with

minimal hardware redesign.

Package (27 x 27 PBGA 336 package)

xxxx

Figure 1. STi5300 low-cost interactive set-top box

IR Tx/Rx

HDD

QPSK ZIF Rx

Transport

stream in

STV0299

and

STB6000

QPSK ZIF Rx

STV0299

and

STB6000

(Optional)

SiLabs

DAA

Smart

Smart

Cards

cards

Transport

stream in

CVBS/YC

VCR

USB

port

RGB

128 Mbit

DDR

STi5300

PSTN

Flash

Rev. 1

September 2005

1/3

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STI5300-DVB相關(guān)型號PDF文件下載

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