鈻?/div>
Ultra high off-isolation:
-80 dB (typ) at 1 Mhz
Ultra low power dissipation:
I
CC
= 0.2
渭A
(max.) at T
A
= 85 擄C
R
PEAK
on
T
n
= 1.30
惟
max (T
A
= 25 擄C)
at V
CC
= 4.3 V
R
PEAK
on
S
n
= 0.55
惟
max (T
A
= 25 擄C)
at V
CC
= 4.3 V
Wide operating voltage range:
V
CC
(opr) = 1.65 to 4.3 V single supply
4.3 V tolerant and 1.8 V compatible threshold
on digital control input at V
CC
= 1.65 to 4.3 V
Typical bandwidth (-3 dB) at 65 MHz on Sn
channel, 58 MHz on the
T
n
channel
Latch-up performance exceeds 100 mA per
JESD 78, Class II
ESD performance exceeds JESD22
2000-V Human body model (A114-A)
The switch Tn is 鈥渙n鈥?(connected to common port
Dn) when the SELn input is held high and 鈥渙ff鈥?/div>
(high impedance state exists between the two
ports) when SELn is held low.
Additional key features are fast switching speed,
break-before-make delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
QFN10L (1.8 x 1.4 mm)
Description
The STG6684 is a high-speed CMOS low voltage
dual analog SPDT (single pole dual throw) switch
or 2:1 multiplexer/de-multiplexer switch fabricated
in silicon gate C
2
MOS technology.
The STG6684 is designed to operate from 1.65 to
4.3 V, making this device ideal for portable
applications.
The SELn inputs are provided to control the
switch operation. The switch Sn is ON (connected
to common ports Dn) when the SELn input is held
low and OFF (high impedance state exists
between the two ports) when SELn is held high.
Table 1.
Device summary
Order code
STG6684QTR
Package
QFN10L (1.8 x 1.4 mm)
Packaging
Tape and reel
January 2008
Rev 1
1/24
www.st.com
24
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