= 0.025鈩?/div>
STANDARD OUTLINE FOR EASY
AUTOMATED SURFACE MOUNT ASSEMBLY
LOW THRESHOLD DRIVE
LOW GATE CHARGE
EXTREMELY LOW FIGURE OF MERIT
(R
DS(on)
* Q
g
)
3
1
2
1
3
DPAK
IPAK
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique 鈥淪ingle Feature
Size鈩⑩€?strip-based process. The resulting transis-
tor shows extremely high packing density for low
on-resistance and low gate charge.
INTERNAL SCHEMATIC DIAGRAM
s
APPLICATIONS
DC-DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(#)
I
D
(#)
I
DM
(
l
)
P
TOT
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
Value
30
30
鹵 16
24
24
96
70
0.47
鈥?55 to 175
175
Unit
V
V
V
A
A
A
W
W/擄C
擄C
擄C
(
q
) Pulse width limited by safe operating area
(#) Current limited by wire bonding
Note:For the P-CHANNEL MOSFET actual polarity of voltages and
current has to be reversed
May 2002
1/8