(on) = 4.1鈩?/div>
EXTREMELY HIGH dv/dt AND CAPABILITY
GATE TO - SOURCE ZENER DIODES
100% AVALANCHE TESTED
VERY LOW GATE INPUT RESISTANCE
GATE CHARGE MINIMIZED
3
1
1
3
2
DPAK
(Add Suffix 鈥淭4鈥?for Tape & Reel)
IPAK
DESCRIPTION
The third generation of MESH OVERLAY鈩?Power
MOSFETs for very high voltage exhibits unsur-
passed on-resistance per unit area while integrat-
ing back-to-back Zener diodes between gate and
source. Such arrangement gives extra ESD capa-
bility with higher ruggedness performance as re-
quested by a large variety of single-switch
applications.
APPLICATIONS
s
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s
WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
q
)
P
TOT
I
GS
V
ESD(G-S)
dv/dt (1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Gate-source Current (DC)
Gate source ESD(HBM-C=100pF, R=1.5K鈩?
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
700
700
鹵 25
2.3
1.45
9.2
55
0.44
鹵50
1.5
3
鈥?5 to 150
150
(1)I
SD
鈮?.3A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
Unit
V
V
V
A
A
A
W
W/擄C
mA
KV
V/ns
擄C
擄C
(鈥?Pulse width limited by safe operating area
April 2001
1/10
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