鈩?/div>
EXCEPTIONAL dv/dt CAPABILITY
LOW GATE CHARGE 100擄C
100% AVALANCHE TESTED
3
1
3
12
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique 鈥淪ingle Feature
Size鈩⑩€?strip-based process. The resulting transis-
tor shows extremely high packing density for low
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a re-
markable manufacturing reproducibility.
D
2
PAK
I
2
PAK
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
HIGH CURRENT, HIGH SPEED SWITCHING
s
SOLENOID AND RELAY DRIVERS
s
MOTOR CONTROL,AUDIO AMPLIFIERS
s
DC-DC & DC-AC CONVERTERS
s
AUTOMOTIVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, Etc.)
s
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
dv/dt (1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
30
30
鹵 20
80
60
320
150
1
7
鈥?55 to 175
(1) I
SD
鈮?04A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
擄C
(
q
) Pulse width limited by safe operating area
February 2003
1/9
next