ST7282A5 - ST7282B5
ROM FROM EPROM
PRELIMINARY DATASHEET
s
s
ST72-Core
Controller/Driver for max. 20
脳
16, 28
脳
8
or 32
脳
4
LCD segments (ST7LCD4)
56 bytes LCD-RAM
864 bytes data RAM
512 bytes EEPROM (eep2a)
32Kbytes program ROM
24 digital I/O (ST7 IO3) with pull up,
interrupt input, analog input, push-pull/
open drain output
36 LCD/IO combi pins (ST7 LCIO1) with
pull-up, interrupt input, push-pull, open
drain output, LCD output
16 bit reload timer (ST7TIM4)
Watchdog Timer (ST7 WD2)
8 bit synchronous serial I/O (ST7SIO)
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Group & Block Sync Module for RDS (ST7
RDS GB)
RDS filter (ST7 RDS FI)
LCD Synchro IN / Out
System Frequency 8.55 MHz
8 bit A/D Converter (ST7ADC2)
s
RDS Demodulator (ST7 RDS BD)
s
n
n
Family
ST7
Issuer Ref.
PG-RO
Chrono
97115
7282A5B5
March 26, 1997
Previous Ref
Page 1/23
Edition
Target C