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ST16C654CJ68 Datasheet

  • ST16C654CJ68

  • 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO

  • 51頁(yè)

  • EXAR   EXAR

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OCTOBER 2003
GENERAL DESCRIPTION
The ST16C654/654D
1
(654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, transmit and receive FIFO trigger levels,
automatic hardware and software flow control, and
data rates of up to 1.5 Mbps. Each UART has a set of
registers that provide the user with operating status
and control, receiver error indications, and modem
serial interface controls. Selectable interrupt polarity
provides flexibility to meet design requirements. An
internal loopback capability allows onboard
diagnostics. The 654 is available in 64 pin TQFP 68
,
pin PLCC and 100 pin QFP packages. The 64 pin
package only offers the 16 mode interface, but the 68
and 100 pin packages offer an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C654CQ64 (64 pin) offers
three
state
interrupt
output
while
the
ST16C654DCQ64 provides continuous interrupt
output. The 100 pin package provides additional
FIFO status outputs (TXRDY# and RXRDY# A-D),
separate infrared transmit data outputs (IRTX A-D)
and channel C external clock input (CHCCLK). The
ST16C654/654D is compatible with the industry
standard ST16C454 and ST16C654/554D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com




A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
FEATURES
鈥?/div>
Pin-to-pin compatible with ST16C454, ST16C554
and TI鈥檚 TL16C554AFN and TL16C754BFN
鈥?/div>
Intel or Motorola Data Bus Interface select
鈥?/div>
Four independent UART channels
s
s
s
s
s
s
s
s
s
s
Register Set Compatible to 16C550
Data rates of up to 1.5 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
鈥?/div>
2.97V to 5.5V supply operation
鈥?/div>
Sleep Mode (200 uA typical)
鈥?/div>
Crystal oscillator or external clock input
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
F
IGURE
1. ST16C654 B
LOCK
D
IAGRAM
2.97V to 5.5V VCC
GND
UART Channel A
64 Byte TX FIFO
UART
Regs
BRG
TX & RX
IR
ENDEC
64 Byte RX FIFO
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
Data Bus
Interface
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
Crystal Osc/Buffer
654 BLK

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