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ST10F168-Q6 Datasheet

  • ST10F168-Q6

  • 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM

  • 74頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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ST10F168
16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
s
HIGH PERFORMANCE CPU
鈥?16-BIT CPU WITH 4-STAGE PIPELINE
鈥?80ns INSTRUCTION CYCLE TIME AT 25MHz
CPU CLOCK
鈥?400ns 16 X 16-BIT MULTIPLICATION
鈥?800ns 32 / 16-BIT DIVISION
鈥?ENHANCED BOOLEAN BIT MANIPULATION
FACILITIES
鈥?ADDITIONAL INSTRUCTIONS TO SUPPORT
HLL AND OPERATING SYSTEMS
鈥?SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
MEMORY ORGANIZATION
鈥?256K BYTE ON-CHIP FLASH MEMORY
鈥?10K ERASING / PROGRAMMING CYCLES
鈥?UP TO 16M BYTE LINEAR ADDRESS SPACE
FOR CODE AND DATA (5M BYTE WITH CAN)
鈥?2K BYTE ON-CHIP INTERNAL RAM (IRAM)
鈥?6K BYTE ON-CHIP EXTENSION RAM (XRAM)
鈥?20 YEAR DATA RETENTION TIME
FAST AND FLEXIBLE BUS
鈥?PROGRAMMABLE EXTERNAL BUS CHARAC-
TE- RISTICS FOR DIFFERENT ADDRESS
RANGES
鈥?8-BIT OR 16-BIT EXTERNAL DATA BUS
鈥?MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS / DATA BUSES
鈥?FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
鈥?HOLD-ACKNOWLEDGE BUS ARBITRATION
SUPPORT
INTERRUPT
鈥?8-CHANNEL PERIPHERAL EVENT CONTROL-
LER FOR SINGLE CYCLE, INTERRUPT DRIVEN
DATA TRANSFER
鈥?16-PRIORITY-LEVEL
INTERRUPT
SYSTEM
WITH 56 SOURCES, SAMPLE-RATE DOWN TO
40ns
TIMERS
鈥?TWO MULTI-FUNCTIONAL GENERAL PUR-
POSE TIMER UNITS WITH 5 TIMERS
鈥?TWO 16-CHANNEL CAPTURE / COMPARE
UNITS.
4-CHANNEL PWM UNIT
SERIAL CHANNELS
鈥?SYNCHRONOUS / ASYNCHRONOUS SERIAL
CHANNEL
鈥?HIGH-SPEED SYNCHRONOUS CHANNEL
PQFP144 (28 x 28 mm)
(Plastic Quad Flat Pack)
s
s
s
s
s
s
s
A/D CONVERTER
鈥?16-CHANNEL 10-BIT
鈥?7.76碌S CONVERSION TIME
FAIL-SAFE PROTECTION
鈥?PROGRAMMABLE WATCHDOG TIMER
鈥?OSCILLATOR WATCHDOG
ON-CHIP CAN 2.0B INTERFACE
ON-CHIP BOOTSTRAP LOADER
CLOCK GENERATION
鈥?ON-CHIP PLL
鈥?DIRECT OR PRESCALED CLOCK INPUT.
UP TO 111 GENERAL PURPOSE I/O LINES
鈥?INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION.
鈥?PROGRAMMABLE THRESHOLD (HYSTERESIS)
IDLE AND POWER DOWN MODES
SINGLE VOLTAGE SUPPLY: 5V
鹵
10%
144-PIN PQFP PACKAGE
s
s
s
s
s
FLASH
XRAM
CPU Core
RAM
PEC
Watchdog
CAPCOM2
s
s
CAPCOM1
P.8
P.0
GPTs
ASC
EBC
PWM
ADC
SSC
P.1
P.4
P.6
P.5
CAN
s
Interrupt controller
OSC
BRG
P.3
BRG
P.7
January 2002
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/74
P..2

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