ST10F166
16-BIT MCU WITH 256K FLASH MEMORY
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High Performance 16-bit CPU with 4-Stage
Pipeline
100 ns Instruction Cycle Time at 20 MHz CPU
Clock
500 ns Multiplication (16
脳
16 bit), 1
碌s
Division
(32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Register-Based Design with Multiple Variable
Register Banks
Single-Cycle Context Switching Support
Up to 256 KBytes Linear Address Space for
Code and Data
1 KByte On-Chip RAM
32 KBytes On-Chip Flash EPROM with Bank
Erase Feature
Protection-Optional Flash Memory
Dedicated Flash Control Register with
Operation Lock Mechanism
12 V External Flash Programming Voltage
Flash Program Verify and Erase Verify Modes
1000 Flash Program/Erase Cycles guaranteed
Programmable External Bus Characteristics for
Different Address Ranges
8-Bit or 16-Bit External Data Bus
Multiplexed or Demultiplexed External Address/
Data Buses
Hold and Hold-Acknowledge Bus Arbitration
Support
512 Bytes On-Chip Special Function Register
Area
Idle and Power Down Modes
8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event
Controller (PEC)
PQFP100
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16-Priority-Level Interrupt System
10-Channel 10-bit A/D Converter with 9.7
碌s
Conversion Time (ST10F166)
16-Channel Capture/Compare Unit
Two Multi-Functional General Purpose Timer
Units with 5 Timers
Two Serial Channels (USARTs)
Programmable Watchdog Timer
Up to 76 General Purpose I/O Lines
Supported by a Wealth of Development Tools
like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards
On-Chip Bootstrap Loader
100-Pin Plastic PQFP Package
February 1996
This is preliminary information from SGS-THOMSON. Details are subject to change without notice.
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