音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

SSTU32865 Datasheet

  • SSTU32865

  • 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIM...

  • 29頁

  • PHILIPS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

SSTU32865
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
applications
Rev. 02 鈥?28 September 2004
Product data sheet
1. General description
The SSTU32865 is a 1.8 V 28-bit 1:2 register speci鏗乧ally designed for use on two rank by
four (2R
脳
4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is
similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTU32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).
The SSTU32865 is packaged in a 160-ball, 12
脳
18 grid, 0.65 mm ball pitch, thin pro鏗乴e
鏗乶e-pitch ball grid array (TFBGA) package, which鈥攚hile requiring a minimum
9 mm
脳
13 mm of board space鈥攁llows for adequate signal routing and escape using
conventional card technology.
2. Features
s
28-bit data register supporting DDR2
s
Fully compliant to JEDEC standard JESD82-9
s
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (i.e. 2
脳
SSTU32864 or 2
脳
SSTU32866)
s
Parity checking function across 22 input data bits
s
Parity out signal
s
Controlled output impedance drivers enable optimal signal integrity and speed
s
Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
s
Supports up to 450 MHz clock frequency of operation
s
Optimized pinout for high-density DDR2 module design
s
Chip-selects minimize power consumption by gating data outputs from changing state
s
Supports Stub Series Terminated Logic SSTL_18 data inputs
s
Differential clock (CK and CK) inputs
s
Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
s
Single 1.8 V supply operation
s
Available in 160-ball 9 mm
脳
13 mm, 0.65 mm ball pitch TFBGA package

SSTU32865相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！