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SST89E554RC-40-I-NJ Datasheet

  • SST89E554RC-40-I-NJ

  • FlashFlex51 MCU

  • 62頁

  • SST   SST

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FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU
Preliminary Specifications
FEATURES:
鈥?8-bit 8051 Family Compatible Microcontroller
(MCU) with Embedded SuperFlash Memory
鈥?SST89E564RD/SST89E554RC is 5V Operation
鈥?0 to 40 MHz Operation at 5V
鈥?SST89V564RD/SST89V554RC is 3V Operation
鈥?0 to 25 MHz Operation at 3V
鈥?Fully Software and Development Toolset
Compatible as well as Pin-For-Pin Package
Compatible with Standard 8xC5x Microcontrollers
鈥?1 KByte Register/Data RAM
鈥?Dual Block SuperFlash EEPROM
鈥?SST89E564RD/SST89V564RD: 64 KByte pri-
mary block + 8 KByte secondary block
(128-Byte sector size)
鈥?SST89E554RC/SST89V554RC: 32 KByte pri-
mary block + 8 KByte secondary block
(128-Byte sector size)
鈥?Individual Block Security Lock
鈥?Concurrent Operation during In-Application
Programming (IAP)
鈥?Block Address Re-mapping
鈥?Support External Address Range up to 64
KByte of Program and Data Memory
鈥?Three High-Current Drive Pins (16 mA each)
鈥?Three 16-bit Timers/Counters
鈥?Full-Duplex Enhanced UART
鈥?Framing error detection
鈥?Automatic address recognition
鈥?Nine Interrupt Sources at 4 Priority Levels
鈥?Watchdog Timer (WDT)
鈥?Programmable Counter Array (PCA)
鈥?Four 8-bit I/O Ports (32 I/O Pins)
鈥?Second DPTR register
鈥?Reduce EMI Mode (Inhibit ALE through AUXR SFR)
鈥?SPI Serial Interface
鈥?TTL- and CMOS-Compatible Logic Levels
鈥?Brown-out Detection
鈥?Extended Power-Saving Modes
鈥?Idle Mode
鈥?Power Down Mode with External Interrupt Wake-up
鈥?Standby (Stop Clock) Mode
鈥?PDIP-40, PLCC-44 and TQFP-44 Packages
鈥?Temperature Ranges:
鈥?Commercial (0擄C to +70擄C)
鈥?Industrial (-40擄C to +85擄C)
PRODUCT DESCRIPTION
SST89E564RD, SST89V564RD, SST89E554RC, and
SST89V554RC are members of the FlashFlex51 family of 8-
bit microcontrollers. The FlashFlex51 is a family of microcon-
troller products designed and manufactured on the state-of-
the-art SuperFlash CMOS semiconductor process technol-
ogy. The device uses the same powerful instruction set and
is pin-for-pin compatible with standard 8xC5x microcontroller
devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST鈥檚 patented and pro-
prietary CMOS SuperFlash EEPROM technology with the
SST鈥檚 field-enhancing, tunneling injector, split-gate mem-
ory cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary Super-
Flash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
漏2001 Silicon Storage Technology, Inc.
S71207-00-000 9/01
555
1
firmware for SST鈥檚 device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
In-Application Programming (IAP) operation. The device is
designed to be programmed 鈥淚n-System鈥?and 鈥淚n-Applica-
tion鈥?on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of bootstrap
loader in the memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via
the 鈥淚AP鈥?operation. An example of bootstrap loader is for
the user鈥檚 reference and convenience only. SST does not
guarantee the functionality or the usefulness of the sample
bootstrap loader. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM pro-
gram memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x 8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST鈥檚 highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

SST89E554RC-40-I-NJ 產(chǎn)品屬性

  • Microchip

  • 8-bit Microcontrollers (MCU)

  • 8051

  • FlashFlex

  • 8 bit

  • 40 MHz

  • 32 KB

  • 1 KB

  • No

  • 4.5 V to 5.5 V

  • PLCC-44

  • SMD/SMT

  • 128 B

  • 4.01 mm

  • SPI, UART

  • 16.66 mm

  • + 85 C

  • - 40 C

  • 32

  • 16 bit

  • No

  • Tube

  • Flash

  • 5.5 V

  • 4.5 V

  • 16.66 mm

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