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SST79LF008-33-C-BZYE Datasheet

  • SST79LF008-33-C-BZYE

  • Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

  • 3537.36KB

  • 252頁

  • SST   SST

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Mobile Platform Controller plus
8 Mbit LPC Firmware Flash
SST79LF008
SST79LF008 Notebook System Controller with 8 Mbit LPC Firmware Flash
Advance Information
FEATURES:
鈥?8 Mbit LPC Firmware Memory SuperFlash device
with integrated LPC Keyboard, System configu-
ration, and Power Management controller
鈥?ACPI 2.0 Compliant
鈥?Conforms to LPC Interface Specification v1.1
鈥?Includes support for Multi-byte Firmware
Memory Read/Write Cycles
- Firmware Memory 1-, 2-, 4-, 16-, and
128-byte Read Cycles
- Firmware Memory 1-, 2-, and
4-byte Write Cycles
鈥?15.7 MB/sec data transfer rate @ 33MHz clock
for Multi-Byte Read
鈥?One ID pin for LPC Firmware Memory Device
selection
鈥?LPC Firmware Memory
鈥?8 Mbit Single Block of on-chip SuperFlash
memory with two Shared-ROM modes
- Mode 1: 7 Mbit (896 KByte) for system BIOS
and 1 Mbit (128 KByte) for 8051 firmware
- Mode 2: 7.5 Mbit (960 KByte) for system BIOS
and 0.5 Mbit (64 KByte) for 8051 firmware
鈥?Uniform 4 KByte Sectors and 64 KByte Blocks
with Erase capability
鈥?19 Lockable Blocks: one 16 KByte Boot Block,
two 8 KByte Parameter Blocks, one 32 KByte
Parameter Block, fifteen 64 KByte Main Blocks
- Block Locking Registers for individual block
Read-Lock, Write-Lock, and Lock Down
protection
鈥?Lockable bottom 4 KByte sector for 8051 boot
firmware
鈥?Erase-Suspend allowing Read or Program of the
other blocks
鈥?Two-Cycle Command Set
鈥?Non-Volatile Registers (NVR)
鈥?64-bit SST Pre-Programmed Identifier
鈥?192-bit OTP User Unique Identifier with Write-
Lock protection
鈥?3 KByte OTP User NVR area (UNVR)
鈥?4 KByte Erasable NVR area (ENVR) with Write-/
Read-Lock protection
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Fast Erase/Program Operations
鈥?Sector-Erase Time: 55 ms (typical)
鈥?Block-Erase Time: 55 ms (typical)
鈥?Word-Program Time: 15 碌s (typical)
鈥?/div>
aLPC mode for Rapid Factory Programming
鈥?Alternate LPC bus (aLPC) for in-system and
factory programming
鈥?Auto Address Increment (AAI)
鈥?Multi-Byte Program
鈥?Chip Rewrite Time: 12 seconds (typical)
Embedded Enhanced 8051 MCU
鈥?3- or 6-clock (selectable) per-instruction cycle
鈥?Up to 33 MHz 8051 operating frequency
鈥?Up to 128 KByte Program Address Space
鈥?256 Byte standard 8051 RAM
鈥?2 KByte on-chip expanded
Data RAM / Executable RAM (Scratch ROM)
鈥?Extended up to 2 KByte Stack Space
鈥?Four Levels of Interrupt Priorities and
Twelve Interrupt Vectors
鈥?Power-saving IDLE and Power-Down modes
鈥?Multiple Maskable Hardware Wake-up Events
(sources include: Hibernation timer, LPC, serial
interfaces, all GPIOs, and others)
LPC Host Interfaces
鈥?One 8042-style legacy KBC interface channel
鈥?Two ACPI EC interface channels
鈥?32 8-bit LPC Host-to-8051 Mailbox Registers
鈥?Programmable Base addresses for all channels
System Interrupts
鈥?IRQ1 and IRQ12 via serialized IRQ Interface
鈥?Two EC SCI event outputs
鈥?SMI via Serialized IRQ2 or SMI event output
Hardware GA20 and CPU Reset Outputs Control
16 x 8 (24 pins) Key Scan Matrix expandable to
16 x 14 (30 pins)
Three Independent PS/2 Ports
鈥?Hardware driven receive and transmit protocols
鈥?Integrated time-out control
Two SMBus controllers/Three SMBus channels
鈥?SMBus 2.0 compliant
鈥?Master and Slave operation
鈥?Internal multiplexer for SMBus channel selection
Full-Duplex Enhanced UART channel
SPI Master/Slave channel
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
漏2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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