4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
004C/008C4 Mb/8 Mb LPC Firmware Flash
Advance Information
FEATURES:
鈥?Organized as 512K x8 / 1M x8
鈥?Conforms to Intel
廬
LPC Interface Specification v1.1
鈥?Support Multi-Byte Firmware Memory Read/
Write Cycles
鈥?Single 3.0-3.6V Read and Write Operations
鈥?LPC Mode
鈥?5-signal LPC bus interface for both in-system
and factory programming using programmer
equipment
鈥?Multi-Byte Read capability allowing 15.6 MB/s
data transfer rate @ 33 MHz PCI clock
- Firmware Memory Read cycle supporting
1, 2, 4, 16, and 128 Byte Read
- Firmware Memory Write cycle supporting
1, 2, and 4 Byte Write
鈥?33 MHz clock frequency operation
鈥?WP#/AAI and TBL# pins provide hardware Write
protect for entire chip and/or top Boot Block
鈥?Block Locking Registers for individual block Read-
Lock, Write-Lock, and Lock-Down protection
鈥?5 GPI pins for system design flexibility
鈥?4 ID pins for multi-chip selection
鈥?Multi-Byte capability registers
(read-only registers)
鈥?Status register for End-of-Write detection
鈥?Program-/Erase-Suspend
Read or Write to other blocks during
Program-/Erase-Suspend
鈥?Two-cycle Command Set
鈥?Security ID Feature
鈥?256-bit Secure ID space
- 64-bit Unique Factory Pre-programmed
Device Identifier
- 192-bit User-Programmable OTP
鈥?Low Power Consumption
鈥?Active Read Current: 12 mA (typical)
- Standby Current: 10 碌A(chǔ) (typical)
鈥?Protected Data Area
鈥?12-KByte Protected Data Area space
鈥?Three 4-KByte User-Programmable flash mem-
ory sectors
鈥?Read-lock, write-lock and lock-down protection
for each sector
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Uniform 4 KByte sectors
鈥?SST49LF004C: 11 Overlay Blocks:
- one 16-KByte Boot Block
- two 8-KByte Parameter Blocks
- one 32-Kbyte Parameter Block
- seven 64-KByte Main Blocks
鈥?SST49LF008C: 19 Overlay Blocks:
- one 16-KByte Boot Block
- two 8-KByte Parameter Blocks
- one 32-Kbyte Parameter Block
- 15 64-KByte Main Blocks
鈥?Fast Sector-Erase/Program Operation
鈥?Sector-Erase Time: 18 ms (typical)
鈥?Block-Erase Time: 18 ms (typical)
鈥?Program Time: 7 碌s (typical)
鈥?Auto Address Increment (AAI) for Rapid Factory
Programming (High Voltage Enabled)
鈥?RY/BY# pin for End-of-Write detection
鈥?Multi-Byte Program
鈥?Chip Rewrite Time: (typical)
- SST49LF004C: 1 seconds
- SST49LF008C: 2 seconds
鈥?Packages Available
鈥?32-lead PLCC
鈥?32-lead TSOP (8mm x 14mm)
鈥?All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF00xC flash memory devices are designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for system firmware applications.
The SST49LF00xC device complies with Intel鈥檚 LPC Inter-
face Specification 1.1, supporting a Burst-Read (up to 128
bytes in a single operation) which enables a 15.6 MByte
per second data transfer. The LPC interface operates with
5 signal pins versus 28 pins of a 8-bit parallel flash memory.
This frees up pins on the ASIC host controller resulting in
lower ASIC costs and a reduction in overall system costs
due to simplified signal routing.
漏200 Silicon Storage Technology, Inc.
S71292-00-000
1/06
1
The SST49LF00xC use a 5-signal LPC interface to support
both in-system and rapid factory programming using pro-
grammer equipment. A high voltage pin (WP#/AAI) is used
to enable Auto Address Increment (AAI) mode. The
SST49LF00xC offers hardware block protection in addition
to individual block protection via software registers for criti-
cal system code and data. A 256-bit Security ID space with
a 64-bit factory pre-programmed unique number and a
192-bit user programmable OTP area as well as 12-KByte
Protected Data Area (PDA) enhances the user鈥檚 ability to
implement new security techniques and data protection
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.