512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
FEATURES:
鈥?Single 2.7-3.6V Read and Write Operations
鈥?Serial Interface Architecture
鈥?SPI Compatible: Mode 0 and Mode 3
鈥?Byte Serial Read with Single Command
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption:
鈥?Active Current: 20 mA (typical)
鈥?Standby Current: 10 碌A (typical)
鈥?Sector or Chip-Erase Capability
鈥?Uniform 4 KByte sectors
鈥?Fast Erase and Byte-Program:
鈥?Chip-Erase Time: 70 ms (typical)
鈥?Sector-Erase Time: 18 ms (typical)
鈥?Byte-Program Time: 14 碌s (typical)
鈥?Automatic Write Timing
鈥?Internal V
PP
Generation
鈥?End-of-Write Detection
鈥?Software Status
鈥?10 MHz Max Clock Frequency
鈥?Hardware Reset Pin (RESET#)
鈥?Resets the device to Standby Mode
鈥?CMOS I/O Compatibility
鈥?Hardware Data Protection
鈥?Protects and unprotects the device
from Write operation
鈥?Packages Available
鈥?8-Pin SOIC (4.9mm x 6mm)
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PRODUCT DESCRIPTION
The SST45VF512, SST45VF010 and SST45VF020 are
manufactured with SST鈥檚 proprietary, high performance
CMOS SuperFlash technology. The Serial Flash is
organized as 16 sectors of 4096 Bytes for SST45VF512,
32 sectors of 4096 Bytes for the SST45VF010 and
64 sectors of 4096 Bytes for the SST45VF020. The
memory is accessed for Read or Erase/Program by the
SPI bus compatible serial protocol. The bus signals are:
serial data input (SI), serial data output (SO), serial clock
(SCK), write protect (WP#), chip enable (CE#), and
hardware reset (RESET#).
The SST45VFxxx devices are offered in 8-pin SOIC
package. See Figure 1 for the pinout.
Device Operation
The SST45VFxxx uses bus cycles of 8 bits each for
commands, data, and addresses to execute operations.
The operation instructions are listed in Table 2.
All instructions are synchronized off a high to low transi-
tion of CE#. The first low to high transition on SCK will
initiate the instruction sequence. Inputs will be accepted
on the rising edge of SCK starting with the most signifi-
cant bit. Any low to high transition on CE# before the input
instruction completes will terminate any instruction in
progress and return the device to the standby mode.
Read
The Read operation outputs the data in order from the
initial accessed address. While SCK is input, the address
will be incremented automatically until end (top) of the
address space, then the internal address pointer auto-
matically increments to beginning (bottom) of the ad-
dress space (00000H), and data out stream will continue.
The read data stream is continuous through all ad-
dresses until terminated by a low to high transition on
CE#.
Sector/Chip-Erase Operation
The Sector-Erase operation clears all bits in the selected
sector to 鈥淔F鈥? The Chip-Erase instruction clears all bits
in the device to 鈥淔F鈥?
Byte-Program Operation
The Byte-Program operation programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (鈥淔F鈥? when initiating a Program
operation. The data is input from bit 7 to bit 0 in order.
Software Status Operation
The Status operation determines if an Erase or Program
operation is in progress. If bit 0 is at a 鈥?鈥?an Erase or
Program operation is in progress, the device is busy. If bit
0 is at a 鈥?鈥?the device is ready for any valid operation. The
status read is continuous with ongoing clock cycles until
terminated by a low to high transition on CE#.
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漏 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
514-1 10/00
S71178
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SST
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